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The drain current of a MOSFET in saturation is given by ID = K (VGS – VR)2 where k is a constant. the magnitude of the transconductance gm is

SbistudyAugust 12, 2020inDigital electronicsLeave a comment

Unit Exercise – 1

The drain current of a MOSFET in saturation is given by I_D = K (V_GS – V_R)² where k is a constant. the magnitude of the transconductance g_m is

(a) K (V_GS – V_T)²
(b) 2K (V_GS– V_T)
(c) I_D/V_GS – V_DS
(d) K (V_GS – V_T/V_GS)²
solution and answer :

(b) Given, I_D = K (V_GS – V_T)²

Transconductance g_m = dI_d /dV_GS|v_{ds = constant}
= d /dV_GS K (V_GS – V_T)²
= 2 K (V_GS – V_T)

(1 mark questions)

In the silicon BJT circuit shown below, assume that the emitter area of transistor Q₁ is half that of transistor Q₂.

The value of current I_O is approximately
(a) 0.5 mA
(b) 2 mA
(c) 9.3 mA
(d) 15 mA

The amplifier circuit shown below uses a silicon transistor. the capacitor c_c can be assumed to be short at signal frequency and the effect of output resistance r_o can be ignored. if c_e is disconnected from the circuit which one of the following statements are true?

(a) The input resistance R_I increases and the magnitude of voltage gain A_V decreases
(b) The input resistance R_I decreases and the magnitude of voltage gain A_V decreases
(c) Both input resistance R_I and the magnitude of voltage gain A_V decrease
(d) Both input resistance R_I and the magnitude of voltage gain A_V increase

Assuming the op-amp to be ideal, the voltage gain of the amplifier shown below, is

(a) -R₂/R₁
(b) -R₃ /R₁
(c) -R₂||R₃/R₁
(d) – (R₂ + R₃ /R₁)

In the following limiter circuit, an input voltage V_I = 10 sin 100 t applied. assume that the diode drop is 0.7 v when it is forward biased. the zener breakdown voltage is 6.8 v.

The maximum and minimum values of the output voltage respectively, are
(a) 6.1 V, – 0.7 V
(b) 0.7 V, – 7.5 V
(c) 7.5 V, – 0.7 V
(d) 7.5 V, – 7.5 V

The correct full-wave rectifier circuit, is
In a transconductance amplifier, it is desirable to have

(a) a large input resistance and a large output resistance
(b) a large input resistance and a small output resistance
(c) a small input resistance and a large output resistance
(d) a small input resistance and a small output resistance

The input impedance (Z_I) and the output impedance (Z_O) of an ideal transconductance (voltage controlled current source) amplifier are

(a) Z_I = 0, Z_O = 0
(b) Z_I = 0, Z_O = ₀₀
(c) Z_I = ₀₀, Z₀ = 0
(d) Z_I = ₀₀, Z_O = ₀₀

An n-channel depletion MOSFET has following two points on its I_D – V_GS curve

(i) V_GS = 0 at I_D = 12 mA and
(ii) V_GS = – 6 V at I_D = 0
Which of the following Q points will give the highest transconductance gain for small signals ?
(a) V_GS = -6 V
(b) V_GS = + 6 V
(c) V_GS = 0
(d) V_GS = 3V

The effect of current shunt feedback in an amplifier is to

(a) increase the input resistance and decrease the output resistance
(b) increase both input and output resistances
(c) decrease both input and output resistances
(d) decrease the input resistance and increase the output resistance

The input resistance R_I of the amplifier shown in figure, is

(a) 30/4 k
(b) 10 k
(c) 40 k
(d) infinite

The cascode amplifier is a multi-stage configuration of

(a) CC-CB
(b) CE-CB
(c) CB-CC
(d) CE-CC

If for a silicon n-p-n transistor, the base to emitter voltage (V_BE) is 0.7 v and the collector to base voltage (V_CB) is 0.2 v, then the transistor is operating in the

(a) normal active mode
(b) saturation mode
(c) inverse active mode
(d) cut-off mode

An ideal op-amp is an ideal

(a) voltage controlled current source
(b) voltage controlled voltage source
(c) current controlled current source
(d) current controlled voltage source

Voltage series feedback (also called series shunt feedback) results in

(a) increase in both input and output impedance
(b) decrease in both input and output impedances
(c) increase in input impedance and decrease in output impedance
(d) decrease in input impedance and increase in output impedance

The circuit given in figure is a

(a) low-pass filter
(b) high-pass filter
(c) band-pass filter
(d) band-reject filter

Assuming V_{CE, SAT} = 0.2 V and B = 50, the minimum base current (I_B) required to drive the transistor in figure to saturation is

(a) 56 uA
(b) 140 uA
(c) 60 uA
(d) 3 uA

Choose the correct match for input resistance of various amplifier configurtions shown below.

Configuration                                                                           input resistance
CB = Common base                                                                LO = Low
CC = Common collector                                                         MO = moderate
CE = Common emitter                                                           HI = high
(a) CB-LO, CC-MO, CE-HI
(b) CB-LO, CC-HI, CE-MO
(c) CB-MO, CC-HI, CE-LO
(d) CB-HI, CC-LO, CE-MO

The circuit shown in figure below is best described as a

(a) bridge rectifier
(b) ring modulator
(c) frequency discriminatory
(d) voltage doubler

If the input to the ideal comparator shown in figure below is a sinusoidal signal of 8 v (peak to peak) without any DC component then the output of the comparator has a duty cycle of

(a) 1/2
(b) 1/3
(c) 1/6
(d) 1/12

If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48 dB and 2 dB respectively then its common mode rejection ratio is

(a) 23 dB
(b) 25 dB
(c) 46 dB
(d) 50 dB

Generally, the gain of a transistor amplifier falls at high frequencies due to the

(a) internal capacitance of the device
(b) coupling capacitor at the input
(c) skin effect
(d) coupling capacitor at the output

In a negative feedback amplifier using voltage-series (i.e.,) voltage-sampling series mixing feedback.(R_I and R_O denote the input and output resistances respectively)

(a) R_I decreases and R_O decreases
(b) R_I decreases and R_O increases
(c) R_I increases and R_O decreases
(d) R_I increases and R_O increase

A 741-type op-amp has a gain bandwidth product of 1 MHz. A non-inverting amplifier using this op-amp and having a voltage gain of 20 dB will exhibit a 3 dB bandwidth of

(a) 50 kHz
(b) 100 kHz
(c) 1000/17 kHz
(d) 1000/7.07 kHz

Three identical RC coupled transistor amplifiers are cascaded. if each of the amplifiers has a frequency response as shown in figure, the overall frequency response is as given in
The current gain of a BJT is

(a) g_mr_o
(b) g_m/r_o
(c) g_mr
(d) g_m/r

MOSFET can be used as

(a) current controlled capacitor
(b) voltage controlled capacitor
(c) current controlled inductor
(d) voltage controlled inductor

The ideal op-amp has the following characteristics

(a) R_I = ₀₀, A = ₀₀, R_O = 0
(b) R_I = 0, A = ₀₀, R_O = 0
(c) R_I = ₀₀, A = ₀₀, R_O = 0
(d) R_I = 0, A = ₀₀, R_O = ₀₀

Consider the following two statements :

Statement 1 A stable multi-vidrator can be used for generating square wave.
Statement 2 Bi stable multi-vibrator can be used for storing binary information.
(a) only statement 1 is correct
(b) only statement 2 is correct
(c) both the statements 1 and 2 are correct
(d) both the statements 1 and 2 are correct

For the ring oscillator shown in figure the propagation delay of each inerter is 100 ps. what is the fundamental frequency of the oscillator output?

(a) 10 MHz
(b) 100 MHz
(c) 1 GHz
(d) 2 GHz

In the differential amplifier shown in figure, if the source resistance of the current source I_EE is infinite then the common mode gain is

(a) zero
(b) infinite
(c) indeterminate
(d) V_m1 + V_m2 /2V_EE

In the circuit of figure below V_O is

(a) -1 V
(b) 2 V
(c) +1 V
(d) +15 V

An amplifier with resistive negative feedback has two left half plane poles in its open-loop transfer function. the amplifier

(a) will always be unstable at high frequencies
(b) will be stable for all frequencies
(c) may be unstable, depending on the feedback factor
(d) will oscillate at low frequencies

If the op-amp in figure below is ideal, then V_O is

(a) zero
(b) (V₁ – V₂) sin ₀₀t
(c) – (V₁ + V₂) sin ₀₀t
(d) (V₁ + V₂) sin ₀₀t

The configuration of figure below is a

(a) precision integrator
(b) hartley oscillator
(c) butter-worth high-pass filter
(d) wien bridge oscillator

A ssume that op-amp of figure below is ideal. if V_I is a triangular wave, then V_O will be,

(a) square wave
(b) triangular wave
(c) parabolic wave
(d) sine wave

For the same AC voltage and load impedance, which of the following statements about rectifier is courrect ?

(a) the average load current in a full-wave rectifier is twice that in a half-wave rectifier
(b) the average load current in a full-wave rectifier is n times in a half-wave rectifier
(c) half-wave rectifier will have a bigger sized transforms compared to full wave rectifier
(d) half-wave rectifier will have a small sized transformer compared to a full wave rectifier

Referring to the figure below. the swithc S is in position 1 initially and steady state conditions exist from time t = 0 and t = t_o. the switch is suddenly thrown into position 2. the current I through the 10 k resistor as a function of time t from t = 0, is (give the sketch showing the magnitudes of the current at t = 0, t = t_o and t = ₀₀)

(a) 1 mA
(b) 2 mA
(c) 3 mA
(d) 4 mA

In figure below the input V_I is a 100 Hz triangular wave having a peak amplitude of 2 V and an average value of zero volt. given that the diode is ideal, the average value of the output V_O is

(a) 0.7
(b) 0.6
(c) 0.5
(d) 0.4

In the circuit of figure below assume that the diodes are ideal and the meter is an average indicating ammeter. the ammeter will read

(a) 0.4 2A
(b) 0.4 A
(c) 0.8 A
(d) 0.4 A

half-wave rectifier uses a diode with a forward resistance R_F. the voltage is V_M sin ₀₀t and the load resistance is R_L. the DC current is given by

(a) V_M/2R_L
(b) V_M /(R_F + R_L)
(c) 2V_M
(d) V_M/ R_L

For small signal AC operation a practical forward biased diode can be modeled as

(a) a resistance and a capacitance in series
(b) an ideal diode and resistance in parallel
(c) a resistance and an ideal diode in series
(d) a resistance

A transistor having a = 0.99 and V_BE = 0.7 is used in the circuit shown in figure below. the value of the collector current will be

(a) 4.327 mA
(b) 5.327 mA
(c) 6.327 mA
(d) 5.508 mA

The following waveforms shown ……………operation of power amplifier.

(a) class-A
(b) class-B
(c) class-C
(d) class-AB

Aiter cascading n stages the overall gain becomes,

(a) A/(1 – j f_1/f)ⁿ
(b) A/(1 – jf/f₁) ⁿ
(c) A/(1 – jf/f₁)^1/n
(d) A/ (1 – jf₁/f)^1/n

For the circuit given below, the base voltage V_B is

(a)0.8 V
(b) 1.697 V
(c) 1.632 V
(d) 0.721 V

Consider the circuit shown in figure below. the transistor parameters are B = 100 and V_A = ₀₀.

If Q point is in the centre of the load the ilne and I_CQ = 0.5 mA the values of V_BB and R_C are
(a) 20 k, 1.2 v
(b) 10 k, 1.45 v
(c) 48 k, 0.95 v
(d) 48 k, 1.45 v

The op-amp shown in figure below, has a very poor open-loop voltage gain of 45 but it is ideal. the gain of the amplifier equals

(a) 5
(b) 4.5
(c) 4
(d) 20

If the transistor parameters are B = 180 and early voltage V_A = 140 V and it is biased at I_CO = 2 mA, the values of hybird parameters, g_m,r and r_o are, respectively

(a) 14 A/V, 2.33 K, 90 K
(b) 14 A/V, 90 K, 2.33 K
(c) 77 mA/V, 2.33 K, 70 K
(d) 77.2 A/V, 70 K, 2.33 K

Voltage gain A_V = V_C/V_S of the given amplifier circuit is

(a) 750
(b) 150
(c) 50
(d) 100

A bipolar amplifier circuit shown below, exhibits the following characteristics:

If there is no early effect then voltage gain of the amplifier for a bias current I_C = 1 mA is
(a) 20
(b) 40
(c) 10
(d) 100

If a resistor is introduced in the emitter of a common emitter (CE) amplifier then

(a) both input impedance and voltage gain increase
(b) input impedance increases and voltage gain decreases
(c) input impedance decreases and voltage gain increases
(d) both input impedance and voltage gain decrease

In the following circuit, voltage drop across R_C and R_E are equal to 20 V_T and 4V_T, respectively. what is the gain of circuit (V_T is thermal voltage assume B is high)

(a) -0.25
(b) -4
(c) -5
(d) -1

In an amplifier response f_t (gain bandwidth product is…………….times greater than f_b (lower cut-off) freqeuncy

(a) B
(b) bandwidth
(c) a
(d) none of these

Transistor transconductance g_m is

(a) directly proportional to current and inversely proportional to temperature
(b) directly proportional to current and directly proportional to temperature
(c) inversaly proportional to current and directly proportional to temperature
(d) inversaly proportional to both current and temperature

JFET cannot provide high voltage gain because of

(a) low values of u
(b) large values of u
(c) large values of g_m
(d) low values of g_m

Consider an n-channel MOSFET with parameters K_n = 0.25 mA/V², V_TN = 1 V, C_GD = 0.04 PF and C_GS = 0.2 PF. The transistor is biased at V_GN = 3 V. the unity gain bandwidth of an FET is

(a) 500 MHz
(b) 350 MHz
(c) 332 MHz
(d) 663 MHz

A 3 stage cascade amplifier of similar FET CS-stages has an overall voltage gain of |1000| and overall bandwidth of 50 x 10⁶ Hz. given, g_m = 15 mA/V, the shunt capacitance for single stage will be

(a) 15 pF
(b) 150 pF
(c) 0.7 pF
(d)2.4 pF

The f_t of a BJT is related to its g_m, C_U and C_U as follows

(a) f_t = C + C_U /g_m
(b) f_t = e (C + C_U)/g_m
(c) f_t = g_m /C + C_U
(d) f_t = g_m /2 (C + C_U)

From a measurement of the rise time of the output pulse of an amplifier whose input is a small amplitude square wave, one can estimate the following parameters of the amplifier

(a) gain-bandwidth product
(b) slew rate
(c) upper 3 dB frequency
(d) lower 3 dB frequency

The first dominant pole encountered in the frequency response of a compensated op-amp is approximately at

(a) 5 Hz
(b) 10 kHz
(c) 1 MHz
(d) 100 MHz

Which of the following circuits are not useful for wave shaping?

(a) clipper
(b) log amplifier
(c) sample and hold circuit
(d) precision rectifier

The output of the op-amp shown below will be, assuming it to be ideal

(a) zero
(b) – (V₁ + V₂)
(c) V₁ – V₂
(d) – (V₁ – V₂)

A boot strap generally incorporates

(a) CE configuration
(b) CB configuration
(c) emitter follower
(d) none of the above

How can we minimize the errors due to input bias current input offset current?

(a) use the resistance R_comp = R_F||R₁
(b) use of op-amp with small ratings of I_los
(c) keep the resistance value as small as possible
(d) all of the above

The purpose of using R_F in the following circuit is

(a) to reduce the gain at low frequency
(b) to reduce the gain at high frequency
(c) to increases the gain
(d) none of the above

Applications of precision diode are
half-wave rectifier
peak detector
window detector

which of the above statements are true?
(a) 1, 2 and 3
(b) 1 and 3
(c) 1 and 2
(d) none of these

The ideal closed-loop voltage gain is

(a) 1
(b) -1
(c) infinite
(d) 50

A current mirror can be used as an active load because

(a) it has low AC resistance
(b) it has high AC resistance
(c) it has high DC resistance
(d) it has low DC resistance

V to I converters are used for
DC and AC voltmeters
photo devices testing
AM communication
diode testing

which of the above staements are true?
(a) 1 and 2
(b) 2 and 4
(c) 1 and 4
(d) 1 and 3

The op-amp of figure below, has very poor open-loop voltage gain of 45 but is otherwise ideal the gain of the amplifier equals

(a) 5
(b) 20
(c) 4
(d) 4.5

In order that circuit of figure helow works properly as differentiator it should be modified to ……….(draw the modified circuit)

An op-amp has an offset voltage of 1 mV and is ideal in all other respects. if this op-amp is used in the circuit shown in figure below, the output voltage will be (select the nearest value)

(a) 1 mV
(b) 1 V
(c) = 1 V
(d) zero

The frequency compensation is used in op-amps to increase its

(a) bandwidth stabilly
(b) frequency gain
(c) amplitude gain
(d) none of these

The circuit shown in figure below is that of

(a) a non-inverting amplifier
(b) an inverting amplifier
(c) an ocilllator
(d) a schmitt trigger

One input terminal of high gain comparator circuit is connected to ground and a sinusoidal voltage is applied to the other input. the output of comparator will be

(a) a sinusoidal
(b) a full rectified sinusoidal
(c) a half rectified sinusoidal
(d) a square wave

The poles of a continuous time oscillators are

(a) imaginary poles
(b) real poles
(c) complex poles
(d) lie on j₀₀ axis

A pulse having a rise time of 40 ns is displayed on a CRO of 12 MHz bandwidth. the rise time of the pulse is observed on the CRO would be approximately equal to

(a) 50 ns
(b) 55 ns
(c) 58 ns
(d) 60 ns

In a triangular wave generator using comparator integrator so that f_o = 2 kHz and V_opp = 7 v, supply voltage = + 15 v, V_sat = + 14 v. R₂ = 10 K and C₁ = 0.05 uF then determine R₁ and R₁

(a) 40 k, 10 k
(b) 10 k, 40 k
(c) 30 k, 30 k
(d) 5 k, 40 k

A 1 st order low-pass butter-worth filter has cut-off frequency of 1 kHz for C = 0.01 uF. now, if the cut-off frequncy has to change by a scaling factor of 0.625. what should be the value of resistor ?

(a) 15.9 k
(b) 25.44 k
(c) 9.95 k
(d) 25.47 k

The phase-shift oscillator in figure below, operates at f = 80 kHz. the value of resistance R_F is

(a) 814
(b) 236
(c) 148
(d) 438

In a hartley oscillator I₁ = 15 mH and C = 50 pF Calculate L₂ for a frequncy of 168 kHz. the mutuat inductance between L₁ and L₂ is 5 uH

(a) 3.1 mH
(b) 2.9 mH
(c) 4.4 mH
(d) 5 mH

For the circuit shown in figure below the true relation is

(a) V₀₁ = 2V₀₂
(b) V_O1 = V_O2
(c) V_O1 = V_O1
(d) 2V_O1 = V_O2
transistor if not given in problem.

The common-emitter current gain of the transistor is B = 75. the voltage V_BE in on state is 0.7 v.the value of I_E and R_C are

(a) 1.46 mA, 6.74 k
(b) 0.987 mA, 3.04 k
(c) 1.13 mA, 5.98 k
(d) none of these

The common-emitter current gain of the transistor is B = 75. The voltage V_BE in on state is 0.7 v. the value of V_BC us

(a) 8.4 v
(b) 6.2 v
(c) 4.1 v
(d) none of these

The circuit shown below is an op-amp based. the ratio V_out/V_in is equal to

(a) 9
(b) 10
(c) 21
(d) 11

In the following circuit of figure below, the region of operation of M₁ is (V_TH = 0.4 V)

(a) linear
(b)saturation
(c) M₁ is off
(d) Cannot be determined
Answers with Solutions
Unit Exercise -1

(b) Applying voltage law for transistor Q₁

0 – 9.3 x 10³ x (I_ref) – V_BE = – 10
I_ref = 10 – V_BE /9.3 x 10³ = 10 – 0.7/9.3 x 10³
= 1 x 10^-3 A
I₀ /I_ref = Emitter area of Q₂ /Emitter area of Q₁
I₀ /I_ref = 2
I₀ = 2 x I_ref = 2 x 1 x 10^-3 = 2 mA

(c) By disconnecting C_E, the circuit becomes shunt series or current series feedback amplifier. in this case, both output resistance (R₀) and voltage gain (A_V) will decrease by factor (1 + AB).
(a) The circuit can be re-arranged as

This is an inverting amplifier
Hence, voltage gain (A_v) = -R₂/R₁

V₀ = V_D + V_Z = 0.7 + 6.8 = 7.5 V
For negative half cycle of input signal V_i diode D₁ is reverse biased and D₂ conducts.
V_O = – V_D = -0.7
Hence, (V_max,V_min) = (7.5 V,- 0.7 V)

(b) Given, I_D = K (V_GS – V_T)²

Transconductance g_m = dI_d /dV_GS|v_{ds = constant}
= d /dV_GS K (V_GS – V_T)²
= 2 K (V_GS – V_T)

(c) For positive cycle of input the diode D₁ and D₃ conduct. for negative cycle of input, the diode D₂ and D₄ conduct.
(a) A practical transconductance amplifier has large input resistance (R_i >> R_S) and presents high output resistance (R_O >> R_L).
(d) As shown in previous solution the ideal transconductance (voltage controlled current source) amplifier has infinite the input impedance (Z_I) and the output impedance (Z_o).
(d)

As shown in curve when V_GS is made more, the I_d increasing rapidly.
Hence, choosing Q point at V_GS = 3 V will give highest transconductance gain.

(d) the input resistance in curent shunt feedback amplifier

R_OR = R_O (1 + BA_I) hence increases by a factor (1 + BA_I).

Form virtual ground, V_A = 0, I_S = V_S – V_A /10 K = V_S /10 K
Input resistance R_I = V_S/I_S = V_S /(V_S/10 K) = 10 K
12 (b)
In cascode amplifier has common emitter (CE) feeding a common base (CB) .

( a) Since, V_BE = 0.7 V, V_CB = 0.2 V

The base emitter junction is forward biased and collector base junction is reverse biased. hence, transistor is operating in normal active mode.

(b) The op-amp output voltage is controlled by input voltage.
(c) In voltage series feedback amplifier

R_IF = R_I (1 + BA_V)
Input resistance increases by a factor (1 + BA_v).
R_OF = R_O / (1 + BA_V)
Output resistance decreases by a factor (1 + BA_V).

This is second order low-pass active filter.

To drive transistor in saturation,
I_B > I_C,sat /B
> V_CC – V_CE,sat/RB
> 3 – 0.2 /1 x 10³ x 50 = 56 uA
I_B _min = 56 uA

(b) The input impedance of

common base = r_e: low, in the range of 20 .
common collector = B (r_e + R_E) high in the range of 100 k
common emitter = Br_e moderate: moderate ; in the range of 1 k.

During positive half cycle, diode D₁ conducts charging capacitor C₁ to a peak voltage V_M and diode D₂ is non-conducting.
During negative half cycle, diode D₂ conducts charging capacitor C₂ to a peak voltage V_M and diode D₁ is non-conducting.
The voltage across capacitors C₁ and C₂ is 2V_m, hence, the circuit behaves as voltage doubler.

V_I = 4 sin _00f
V_REF = 2 V
V₀ = V_I; V_I > V_REF
4 sin _oof = 2
sin _00t 1/2
_00t = 6 , 5/6
Duty cycle = t_on/t = 6 – 6 /2 = 4 /12 = 1/3

= Differetial voltage gain(A_D) /Common mode gain (A_C)
In decibal, we can write
(CMRR) _dB = (A_d) _db – (A_C) _dB
= 48 – 2 = 46 dB

(a) At high frequency internal capacitance effects come into the picture, that’s why it effects the gain of the amplitude.
(c) In voltage-series feedback amplifier

R_IF = R_I (1 + BA_V)
R_OF = R_O /(1 + BA_V)
Hence, R_I increases and R_O decreases by a factor (1 + BA_V).

(b) Given, (Given)_dB = 20 dB

20 log (given) = 20
given = 10
gain bandwidth product = 1 x 10⁶ Hz
gain x 3 dB bandwidth = 1 x 10⁶
10 x 3 dB bandwidth = 1 x 10⁶
3 dB bandwidth = 10⁵ Hz = 100 kHz

given , lower cut-off frequency f_l = 20 Hz
upper cut-off frequency f_h = 1 kHz
when n identical amplifiers are cascaded, then overall lower cut-off frequency,
f_L = f_L /2^VN – 1
For n = 3,
f_l = 20 /2^1/3 – 1
= 39.22 – 40 Hz
overall upper cut-off frequency
f^*_H = f_H x 2^1/n – 1
n = 3
= 1 x 2^1/3 – 1
= 0.5 kHz
hence, overall bandwidth decreases.

Common emitter current gain B = g_mr
where, g_m = transconductance
r = small signal resistance between base and emitter.

(b) In MOSFET, the gate and the channel regions form a parallel-plate capacitor with oxide layer act as a charge on the top plate of capacitor and corresponding opposite charge formed in the induced channel, an electric field thus develop which controls the amount of charge (current) in the channel. hence, MOSFET can be used as voltage controlled capacitor.
(a) Characteristics of ideal op-amp
Infinite input impedance
Zero output impedance
Zero common-mode gain or infinite common-mode rejection
Infinite open-loop gain A
Infinite bandwidth
(c) Astable multi-vibrator has no stable state and it can be used for generating square wave and triangle waveform.

Example oscillator.
Bistable multi-vibrator has two stable output stages. the circuit can remain in either stable state indefinitely and move to another stable state only when appropriately triggered.
Example flip-flop (used for storing information).

In general, a ring oscillator with N inverters (where, N must be odd will oscillate with period of 2Nt_p and frequency 1 /2NT_P ; where t_p is propagation delay of each inverter.
Here, N = 5; t_p = 100 x 10^-12 s
Fundamental frequency of output
= 1 / 2 x 5 x 100 x 10^-12
= 1 x 10⁹ Hz = 1 GHz

For differential amplifier
CMRR = A_D /A_C = 2g_mR_EE
where, CMRR = Common mode rejection ratio
A_D = differential gain
A_C = common mode gain
CMRR will be large, if R_EE is large.
if R_EE ₀₀, the CMRR ₀₀ : A_CM = 0
i.e., no common mode component appears at the output.

As positive feedback is applied hence, the op-amp is forced to operate in saturation region. since, input is applied in positive terminal, output voltage is + V_SAT, i.e., + 15 V.

Hence, open-loop transfer function
G (S) = 1 /(s + a) (s + b)
and H(s) be feedback function.
closed-loop transfer function = V(s + a) (s + b)/1 + H|(s + a) (s + b)
Characteristic equation
= (s + a) (s + b) + h
= s² + (a + b) s + ab + h
roots = -(a + b) + (a + b)² – 4 (ab + h)/2
Hence, closed-loop transfer function depends upon H, amplifier may be unstable for large value of H.

from virtual ground concept V_A = V_B = 0
Applying kirchhoff’s current law at node B,
c d/dt (V_S sin _00t – 0) + c d/dt (V₂ sin _00t – 0)
= c d/dt ( 0 – V_o
d/dt (V₁ sin _oot) + d/dt (V₂ sin _00t) = – d/dt V_O
integrating,
V₀ = – V₁ sin _00t – V₂ sin _00t
= – (V₁ + V₂) sin _00t

Rearranging the circuit component,
The configuration is wien bridge oscillator, the bridge has series RC network in one arm and a parallel RC network in the adjoining arm. in the remaining two arms of the bridge resistors R₁ and R₂ are connected.
Resonant frequency f_o = 1 / 2RC
For substained oscillation, R₂ = 2R₁,

from virtual ground conecept
V_A = V_B = 0
Applying kirchhoff’s current law at node B,
c d/dt (V_I – 0) = (0 – V₀)/R
V₀ = – RC dv_i/dt
hence, output is differentiation of input waveform, when triangular wave is input, then square wave is output.

I_av for full wave rectifier = 2I_m
I_av for half wave rectifier = I_m

Assume ideal diode at t = 0, t = t_o
I = 20/10 k = 2 mA

V_av = 0.7 V

The meter will read during positive half cycle V_av = V_m/R
= 4 /z x 10 x 10³ = 0.4 /z mA

V_m / z (R_F + R_L)

For small signal AC operation practical forward-biased diode equivalent contains a resistor.

By KVL
(I_C + I_B) 1 K + 10 KI_B + 0.7 + (I_B + I_C) 1 K = 12
B = a/1 – a = 0.99 /1 – 0.99 = 99
(I_C + I_C/99) 10³ + 10 x 10³ x I_C /99 + 0.7 + (I_C + I_C/99) 10³ = 12
100I_C/99 x 10³ + 10 x 10³ x I_C/99 + 100I_C/99 x 10³ +0.7 =12
100 x 10³/99 I_C + 10 x 10³ I_C + 100 x 10³/99 I_C = 11.3
I_C = 5.327 mA

Let V₁ be the voltage at n-terminals of diode,
V₁ = 15 x 1/2 + 1 = 5 V
for V_I < 5.7 V, V₀ = V_I
V₁ – 15/2K + V₁/1K + V₀ – V_I/1K = 0
3V₁ + 2V₀ – 2V_I = 15
V₀ = V_I + 0.7
5V₀ – 2V₁ = 15 + 2.1 = 17.9
V₀ = 0.4, V_I + 342

For V_S > 0, when D₁ is off current through D₂ is
I = 10 -0.7 /10 + 10 = 0.465 mA
V_O = 10ki = 4.65 V
V_O = V_S, for 0 < V_S < 4.65 V
For negative values of V_S, the output is negative of positive part.

The diode conducts (zero resistance) when V_I < 2.5 V and V_O = V_I Diode is open (2 m resistance) when V_I = 2.5 V and V_O = 2.5 + V_I – 2.5 /3 = 5 V

Class AB

A/(1 – j f_i/f)ⁿ

The base current I_B is
I_B = V_CC – V_BE/R_B + BR_E
= 10 – 1.6 /3.3 x 10⁶ + 100 x 390 = 2.51 uA
I_C~ I_E = BI_B
V_E = 0.251 x 390 = 0.097 V
V_B = V_E + V_BE
= 1.697 V

V_ECQ = 1/2 V_CC 10 V
V_ECQ = 20 – I_CQR_C = 10
20 – (0.5 mA) R_C = 10
R_C = 20 K
I_BQ = I_CQ/B = 0.5 /100 = 5 uA
V_EB(ON) + I_BQR_B = V_BB
0.7 + (5 u)(100 k) = 1.2 V

Op-amp shown in the figure has a very poor open loop voltage gain of 45 but otherwise ideal. the gain of amplifier will be
V_O = A(V_L – V_A) = 45(V_L – V_A)
At node, V_A/2 + V_A – V_O /8 = 0
5V_A = V_O
V_A = V_O/5
V_O = 45 V_L – 45V_A = 45V_L – 9V_O
10V_O = 45V_L
A = V_O /V_L = 4.5

g_m = I_CQ/V_T = 2 m/0.0259 = 77.2 mA/V
r = BV_T/I_CQ = B/g_m = 180/77.2 = 2.33 k
r_o = V_A/I_CQ = 140/2 m = 70 k

By DC analysis of the amplifier circuit I_C = I_E = 0.5 mA (since B is high)
so, V_C = 5 – 7.5 x 0.5 = 1.25 V
g_m = I_C/V_T = 0.5 mA/25 mV = 20 mA/V
Small siganal equivalent circuit
V = – V_I
Output voltage V_C is given as
V_C = – V_M V x 7.5 = g_mV_S x 7.5
A_V = V_C/V_S = g_m x 7.5 = 20 x 7.5 = 150

I_C = I_S exp (V_BE/2V_T)
Transconductance g_m = I_C/V_BE = I_C/2V_T
Output impedance
R_OUT = R_C (since, there is no early effect)
equivalent circuit is
Voltage gain is
|V_O/V_IN| = g_mR_C = I_CR_C/2V_T = (1 mA)(1 K)/(2) 0.025 V) = 20

CE amplifiers with and without emitter resistance are shown in the following figure
input impedance. R_IN = r
input impedance R_in [r + (B + 1)]R_E
So, emitter degeneration increases the input impedance of CE stage
Voltage gain is
A_V = g_mR_C/R_C (with emitter resistance)
A_V = R_C (with emitter resistance)
1/g_m + R_C
So, voltage gain decrease.

By small signal analysis of the given circuit voltage gain
A_V = – R_C
1 /g_m + R_E (B >> 1)
= – R_C = – R_CI_C/R_EI_C + V_T
R_E + V_T/I_C
B is large, so I_C ~ I_E
A_V = – R_CI_C/R_EI_E + V_T
= -20V_T/4 V_R + V_R = – 20 /5 = -4

f_t = Bf_b

g_m = |I_C|/V_T

u = g_mr_d and as g_m is very low in JFET, therefore JFET cannot provide high voltage gain.

The transconductance is
g_m = 2k_n (V_GN – V_TN) = 1 mA/V
The unity gain bandwidth is
f_t = g_m /2 (C_gs + C_gd) = 663 MHz

gian of 3 stage = 1000
single stage gain = 10
also bandwidth of single stage
= 50 M /2^1/n – 1 = 98.07 MHz
2^1/n – 1, where n = 3, hence 0.51
now, A_V = 10 = g_mR_D
R_D = 666.66
BW ~ f_h = 1 /2CR_D
C = 1 / 2f_hR_D = 2.4 pF

f_r = g_m/ 2 (c + c_u)

t_r = 0.35/f_h
where, f_h = upper 3 dB frequency.

The first dominant pole encountered in the frequency response of a compensated op-amp is approximately at 5 Hz.

Log amplifier has output which is proportional to the logarithm of input voltage where no wave shaping takes place.

The circuit acts as an inverting summer
V_O = – L /L_E V₁ + L/L V₂
= – (L/L_E V₁ + L/L V₂)
= – (V₁ + V₂)

A boot strap generally incorporates emitter follower.

To minimize error.
R_comp = R_P||R₁, small rating of I_ios and running R small.

The above circuit is a practical integrator circuit which is used obtain stability in the integrator.

Procisio diodes application are half wave rectifier and peak director.

V₊ = V_I, V_– = V_I = V_O, V_O/V_I = 1

It has high AC resistance.

In DC and AC voltmeters as well as diode testing applications, very little current is required. As input impedance of non-inverting ampliifer is very high, V to I circuit has the advantage of drawing little current from source.

op-amp shown in the figure has very poor open loop voltage gain of 45 but it is otherwise ideal. the gain of amplifier will be
V_O = A(V_B – V_A) = 45 (V_B – V_a)
At node V_A/2 + V_A – V_O/8 = 0
5V_A = V_O
V_A = V_O/5
V_O = 45V_B – 45V_A
= 45V_B – 9V_O
10V_O = 45V_B
A = V_O/V_B = 4.5

V_O = V_off x A_V
= 1 x 10^-3 x 1 M/1 K
= + 1 V
Offset is always + + 1 v

Bandwidth stability.

V_A = R₂/R₁ + R₂ V_O
Output V_O will change its stage everytime when input voltage crosses the threshold levels.
V_UT = R₂ /R₁ + R₂ x V_SAT
V_LT = R₂/R₁ + R₂ x – V_SAT

Imaginary poles

Rise time of CRO = 0.35/12 x 10⁶ = 29.17 ns
total time t_s = t²_ro + t²_ro
= (29.17)² + (40)²
= 4.95 x 10^-8 = 50 ns

The peak to peak voltage is given by
V_OPP = 2 (R₂/R₃) V_SAT
7 = 2 (R₂/R₃) (14)
R₂ = R₃/4
R₂ = 10 K R₃ = 40 K
Now, the frequency of oscillation is
f_o = R_E/4R₁R₂C₁
2 K = 40 K/4 x 10 x R₁C₁
C₁ = 0.05 uF R₁ = 10 K

The frequency scaling factor is
0.625 = new frequency /original frequency = f_new/1 k
f_new = 625 Hz
also f_original = 1/2RC R = 1/2fC = 15.92 K
R_new = (scase factor)*R
= 0.625 x 15.92 k = 9.95 k

oscillation frequency,
f = 1/2 6RC
80 K = 1 /2 6R(100)
R = 1/(80 K) (2 6)(100) = 8.12 K
R_F/R = 29 [for RC phase shift oscillator, minimum, gain must be 29]
R_F = (8.12 K) (29) = 236 K

f = 1/2 (L_eqC)
L_EQ = L₁ + L₂ + 2 M
168 x 10³ = 1 /2 [L_eq x 50 x 10^-12]
L_eq = 17.95 mH
17.95 x 10^-3 = 15 x 10^-3 + L₂ + 5 x 10^-6
L₂ = 2.945 mH

At second stage input to both op-amp circuit is same the upper op-amp circuit is buffer having gain A_V = 1. lower op-amp circuit is inverting amplifier having gain
A_V = – R/R = -1
V₀₁ = – V₀₂

I_E = 12 – 0.7/10 K I_E = 1.13 mA
I_C (75/75 + 1) (1.13) = 1.12 mA
V_CE = 12 – 1.13 x 10 – 1.12 R_C – (-12) = 6 V
R_C = 5.98 K

8 = 10 x (75 + 1) I_B + 0.7 + 10I_B – 2
I_B = 9.3 /10 + 760 = 12.08 uA
I_C = BI_B = 0.906 mA
I_E = (B + 1) I_B = 0.918 mA
8 = 10(0.918) + V_EC + 3(0.906) – 8
V_EC = 4.1 V

V_O/V_IN = 1 + R_F/R₁
= 1 + 100 /10 = 1 + 10 = 11

In the given circuit
V_GS = V_G – V_S = 1.5 – 0.5 = 1V
V_DS = V_D – V_S = 2 – 0.5 = 1.5 V
V_DS(SAT) = V_GS – V_TH = 1 – 0.4 = 0.6 V
Here, V_DS > V_DS(SAT) and V_GS > V_TH
SO, M₁ is in saturation region