In a full-wave rectifier using two ideal diodes, VDC and Vm are the DC and peak values of the voltage, respectively across a resistive load

45. In a full-wave rectifier using two ideal diodes, V_DC and V_m are the DC and peak values of the voltage, respectively across a resistive load. if PIV is the peak inverse voltage of the diode, then the appropriate relationships for this rectifier are

45. In the voltage regulator shown in figure, the load current can vary from 100 mA to 500 mA. Assuming that the zener diode is ideal (i.e.,) the zener knee current is negligibly small and zener resistance is zero in the breakdown region), the value of R is

(a) 7
(b) 70
(c) 70/3
(d) 14

47. An amplifier without feedback has a voltage gain of 50, input resistance of 1 k and output resistance of 2.5 k. the input resistance of the current-shunt negative feedback amplifier using the above amplifier with a feedback factor of 0.2, is

(a) 1/11 k
(b) 1/5 k
(c) 5 k
(d) 11 k

48. In the amplifier circuit shown in figure, the values of R₁ and R₂ are such that the transistor is operating at V_CE = 3 V and I_C = 1.5 mA when its B is 150. for a transistor with B of 200, then operating point (V_CE,I_C) is

(a) (2 V, 2 mA)
(b) (3 V, 2 mA)
(c) (4 V, 2 mA)
(d) (4V, 1 mA)

49. The oscillator circuit shown in figure has an ideal inverting amplifier. lts frequency of oscillation (in Hz) is

(a) 1/(2 6 RC)
(b) 1/( 2RC)
(c) 1/ (6RC)
(d) 6/ (2RC)

50. The output voltage of the regulated power supply shown in figure, is

(a) 3V
(b) 6 V
(c) 9 V
(d) 12 V

51. The action of a JFET in its equivalent circuit can best be represented as a

(a) current controlled current source
(b) current controlled voltage source
(c) voltage controlled voltage source
(d) voltage controlled current source

52. If the op-amp in figure is ideal, the output voltage V_OUT will be equal to

(a) 1 V
(b) 6 V
(c) 14 V
(d) 17 V

53. Three identical amplifiers with each one having a voltage gain of 50, input resistance of 1 k and output resistance of 250 are cascaded. the opencircuit voltage gain of the combined amplifier is

(a) 49 dB
(b) 51 dB
(c) 98 dB
(d) 102 dB

54. An ideal sawtooth voltage waveform of frequecy 500 Hz and amplitude 3 V is generated by charging a capacitor of 2 uF in every cycle. the charging requires

(a) Constant voltage source of 3 V for 1 ms
(b) Constant voltage source of 3 V for 1 ms
(c) Constant voltage source of 3 mA for 1 ms
(d) Constant current source of 3 mA for 2 ms

55. An amplifier using an op-amp with a slew rate (sr) = 1V/us has a gain of 40 dB. if this amplifier has to faithfully amplify sinusoidal signals from DC to 20 KHz without introducing any slew rate induced distortion, then the input signal level must not exceed

(a) 795 mV
(b) 395 mV
(c) 79.5 mV
(d) 39.5 mV

56. The circuit in figure employs positive feedback and is intended to generate sinusoidal oscillation. if at a frequency f_o; B(f) = V_F (F) / V_O(F) = 1/6 <0⁰, then to sustain oscillations at this frequency

(a) R₂ = 5R₁
(b) R₂ = 6R₁
(c) R₂ = R₁/6
(d) R₂ = R₁/5

57. A zener diode regulator in figure is to be designed to meet the specifications I_L = 10 mA, V_O = 10 V and V_in varies from 30 V to 50 V. the zener diode has V_Z = 10 V and I_zk (knee current) = 1mA. for satisfactory operation

(a) R < 1800
(b) 2000 < R < 22000
(c) 3700 < R < 4000
(d) R < 4000

58. The voltage gain A_V = V_O/V_I of the JFET amplifier shown in figure is

(a) + 18
(b) – 18
(c) + 6
(d) – 6

59. An n-p-n BJT has g_m = 38 mA /V, C_u = 10 ^-14 F, C = 4 x 10 – ¹³ F^, and DC current gain B₀ = 90. for this transistor f_t and f_b are

(a) f_t = 1.64 x 10⁸ Hz and f_b = 1.47 x 10¹⁰ Hz
(b) f_t = 1.47 x 10¹⁰ Hz and f_b = 1.64 x 10⁸ Hz
(c) f_t = 1.33 x 10¹² Hz and f_b = 1.47 x 10¹⁰ Hz
(d) f_t = 1.47 x 10¹⁰ Hz and f_b = 1.33 x 10¹² Hz

60. The transistor shunt regulator shown in figure has a regulated output voltage of 10 v, when the input voltage varies from 20 v to 30 v. the relevant parameters for the zener diode and the transistor are V_Z = 9.5, V_EE = 0.3 V, B = 99. Neglect the current through R_B. then, the maximum power dissipated in the zener diode (p_z) and the transistor (p_t) are

(a) P_Z = 75 MW, P_T = 7.9 W
(b) P_Z = 85 mW, P_T = 8.9
(c) P_Z = 95 mW, P_T = 9.9 W
(d) P_Z = 115 mW, P_T = 11.9

61. The oscillator circuit shown in figure is

(a) Hartley oscillator with f_oscillation  = 79.6 MHz
(b) Colpitts oscillator with f_oscillation = 79.6 MHz
(c) Hartley oscillator with f_oscillation = 159.2 MHz
(d) Colpitts oscillator with f_oscillantio = 159.2 MHz

62. The inverting op-amp shown in figure has an open-loop gain of 100. the closed-loop gain V_O/V_S is

(a) – 8
(b) – 9
(c) – 10
(d) – 11

63. In figure, assume the op-amps to be ideal. the output V_O of the circuit is

(a) 10 cos (100t)
(b) 10 cos (100t) dt
(c) 10^-4 cos (100t) dt
(d) 10^-4 d/dt cos (100t)

64. In the circuit of figure, assume that the transistor is in active region. it has a large B and its base-emitter voltage is 0.7 V. the value of I_C is

(a) indeterminate since R_C is not given
(b) 1 mA
(c) 5 mA
(d) 10 mA

65. If the op-amp in figure has an input offset voltage of 5 mV and an open-loop voltage gain of 10000, then V_O will be

(a) zero
(b) 5 mV
(c) + 15 V or – 15 V
(d) + 50 V or – 50 V

66. The CMRR of the differential amplifier of figure is equal to

(a) infinite
(b) zero
(c) 900
(d) 1800

67. Which of the following statements is correct for basic transistor amplifier configurations?

(a) CB amplifier has low input impedance and a low current gain
(b) CC amplifier has low output impedance and a low current gain
(c) CE amplifier has very poor voltage gain but very high input impedance
(d) The current gain of CB amplifier is higher than the current gain of CC amplifier

68. The JFET in the circuit shown in figure has an I_DSS = 10 mA and V_P = 5 V. the value of the resistance R_S for a drain current I_DS = 6.4 mA is (select the nearent value)

(a) 150
(b) 470
(c) 560
(d) 1 k

69. A class-A transformer coupled, transistor power amplifier is required to deliver a power output of 10 w. the maximum power rating of the transistor should not be less than

(a) 5 W
(b) 10 W
(c) 20 W
(d) 40 W

70. For the 2 N 338 transistor, the manufacturer specifies P_MAX = 100 mW at 25^o C free air temperature and the maximum junction temperature, T_max = 125⁰C its thermal resistance is

(a) 10^oC/W
(b) 1000^oC/W
(c) 100^oC/W
(d) none of these

71. An amplifier has an open loop gain of 100 and its lower and upper cut-off frequency of 100 Hz and 100 kHz respectively. A feedback network with a feedback factor of 0.99 is connected to the amplifier. the new lower and upper cut -off frequencies are

(a) 10 MHz 1 Hz
(b) 1 Hz, 10 MHz
(c) 10 Hz, 10 Hz
(d) none of these

72. Match the list I with list ll and find the correct answer using the codes given below the lists.
73. A power amplifier delivers 50 W output at 50% efficiency. the ambient temperature is 25⁰C if the maximum allowable junction temperature is 150⁰C, then the maximum thermal resistance that can be tolerated is

(a) 7⁰C/W
(b) 6 ⁰ C/W
(c) 5 ⁰ C/W
(d) 4 ⁰ C/W

74. A change in the value of the emitter resistance R_E in a difference amplifier

(a) affects the difference mode gain A_D
(b) affects the common mode gain A_c
(c) affects both A_d to A_c
(d) does not affect neither A_d nor A_c

75. To obtain very high input and output impedances in a feedback amplifier, the topology mostly used is

(a) voltage series
(b) current series
(c) voltage shunt
(d) current shunt

76. The common emitter short circuit current gain B of a transistor

(a) is a monotonically increasing function of the collector current I_C
(b) is a monotonically decreasing function of I_C
(c) increases with I_C for low I_C reaches a maximum and then decreases with furter increase in I_C
(d) is not a function of I_C

77. Match the list l with list ll and find the correct answer using the codes given below the lists.

List l                                                             List ll

1. Voltage series configuration 1. increase input impedance
2. current shunt configuration       2. decrease input impedance
3. increases closed-loop gain
4. leads to oscillation

Codes
P                                             Q
(a) 2                                               3
(b) 1                                               3
(c) 1                                                4
(d) 4                                                3

78. In a common emitter BJT amplifier, the maximum usable supply voltage is limited by

(a) avalanche breakdown of base-emitter junction
(b) collector- base breakdown voltage with emitter open (V_CBO)
(c) collector – emitter breakdown voltage with base open (V_CBO)
(d) Zerer breakdown voltage of the emitter-base junction

79. A cascade amplifier stage is equivalent to

(a) a common emitter stage followed by a common base stage
(b) a common base stage followed by an emitter follower
(c) an emitter follower stage followed by a common base stage
(d) a common base stage followed by a common emitter stage

80. In the BJT amplifier shown in figure, the transistor is biased in the forward active region putting a capacitor across R_E will

(a) decrease the voltage gain and decrease the input impedance
(b) increase the voltage gain decrease the input impedance
(c) decrease the voltage gain and increase the input impedance
(d) increase the voltage gain and increase the input impedance

81. A multistage amplifier has a low-pass response with three real poles at s = – ₀₀₁ – ₀₀₂ and ₀₀₃. the approximate overall bandwidth B of the amplifier will be given by

(a) B = ₀₀₁ + ₀₀₂ + ₀₀₃
(b) 1/B = 1/₀₀₁ + 1/₀₀₂ + 1/₀₀₃
(c) B = (₀₀₁ + ₀₀₂ + ₀₀₃) ^1/3
(d) B = ₀₀₁² + ₀₀₂² + ₀₀₃²

82. In a shunt-shunt negative feedback amplifier as compared to the basic amplifier

(a) both input and output impedances decrease
(b) input impedance decreases but output impedance decreases
(c) input impedance increases but output impedance decreases
(d) both input and output impedances increase

83. A distorted sinusoid has the amplitudes A₁, A₂, A_{3 …………..} of the fundamental second harmonic, third harmonic, ………. respectively. the total harmonic distortion is

(a) A₂ + A₃ + ….. / A₁
(b) A₂² + A₃² + ….. / A₁
(c) A₂² + A₃² + ……. / A₁² + A₂² + A₃²
(d) A₂² + A₃² + … / A₁

84. In a differential amplifier , CMRR can be improved by using an increased

(a) emitter resistance
(b) collector resistance
(c) power supply voltage
(d) source resistance

85. The circuit of figure is an example of feedback of the following type

(a) current series
(b) current shunt
(c) voltage series
(d) voltage shunt

86. In the MOSFET amplifier of figure and the signal outputs V₁ and V₂ obey the relationship

(a) V₁ = V₂/2
(b) V₁ = – V₂/2
(c) V₁ = 2V₂
(d) V₁ = – 2V₂

87. Two identical FETs, each characterized by the parameters g_m and r_d are connected in parallel. the composite FET is then characterized by the parameters

(a) g_m/2 and 2r_d
(b) g_m/2 and r_d/2
(c) 2g_m and r_d/2
(d) 2g_m and 2r_d

88. Negative feedback in an amplifier

(a) reduces gain
(b) increases frequency and phase distortions
(c) reduces frequency and phase distortions
(d) increases noise

89. In the cascade amplifier shown in the figure, if the commone -emitter stage (Q₁) has a transconductance g_m1 and the common base stage (Q₂) has a transconductance g_m2 then the overall transconductance g (I_O / V_I) of the cascade amplifier is

(a) g_m1
(b) g_m2
(c) g_m1/2
(d) g_m2/2

90. Crossover distortion behaviour is characteristic of

(a) class-A output stage
(b) class-B output stage
(c) class-AB output stage
(d) common base output stage

91. An n-p-n transistor (with C = 0.3 pF) has a unity gain cut off frequency f_t or 400 MHz at a DC bias current I_C = 1 MA . the vaule of its C_u (in pF ) is approximately (V_T = 26 mV)

(a) 15
(b) 30
(c) 50
(d) 96

92. An amplifier has open-loop gain of 100, an input impedance of 1 k and an output impedance 100 a feedback network with a feedback factor of 0.99 is connected to the amplifier in a voltage series feedback mode. the new input and output impedances respectively, are

(a) 10 and 1
(b) 10 and 10
(c) 100 k and 1
(d) 100 k and 1 k

93. An amplifier is assumed to have a single-pole high-frequency transfer function. the rise time of its output response to a step function input is 35 ns. the upper 3dB frequency (in MHz) for the amplifier to a sinusoidal input is approximately at

(a) 4.55
(b) 10
(c) 20
(d)28.6

94. the circuit of figure uses an ideal op-amp. for small positive value of V_in the circuit works as

(a) a half- wave rectifier
(b) a differentiator
(c) a logarithmic amplifier
(d) an exponential amplifier

95. Assume that the operational amplifier in figure is ideal. the current l through the 1 k resistor is

(a) – 4 mA
(b) – 5 mA
(c) – 5 mA
(d) 4 mA
Unit Exercise – 2 answer key with solution 

45. (d)

As zener current is negligible small and zener resistance is zero.
I_L = 12 – 5 /R = 7/R
At    I_L = 100 mA,
= 100 mA = 7/R
R = 70
At      I_L = 500 mA,
R = 14
Minimun value of R = 14

46. (b)

In full-wave rectifer,   V_DC = 2V_m
PIV  = 2V_m

47. (a)

the input resistance of current shunt feedback decreases by factor (1 + AB)
R_IF + R_I/1 + AB = 1 K /1 + 50 x 0.2 = 1/11 k

48. (a)

For B, = 150
Applying KVL,
V_CC – I_C1R₂ – V_CE1 = 0
Putting the value,
R₂ = 2 K
I_B1 = I_C1 /B₁ = 1.5 mA/150 = 0.01 mA
For   B = 200,
I_C = BI_B
= 200 x 0.01 = 2 mA
V_CE2 = V_CC – I_C2 R₂
V_CE = 2 V

49. (a)

one RC pair given phase shift 60⁰ and hence total phase shift will be 180⁰.
this is a RC phase shift oscillator.
f = 1/2  6 RC

50. (c)

As zener diode is in breakdown.
the voltage of non-inverting terminal is V. From virtual ground concept, the voltage of inverting terminal is 3 V.
hence,   V_O  = 60 /20 x 3 = 9 V

51. (d)

In JFET. the drain current is controlled by the charge induced in the channel by voltage applied at gate terminal. hence, it can be treated as voltage controlled current source.

52. (b)

From virtual ground concept,
V_A = V_B = 8/3
Applying KCL at node A,
2 – 8/3 8/3 – V_O
1 K = 5 K
V₀ = 6 V

53. (d)

The open circuit voltage gain of combined amplifier,
AV = AV₁ . AV₂ . AV
= (50)³
Taking logarithmic
20 log AV = 20 log (50)³ = 60 log 50
= 102 dB

54. (d)

V_C = 1/C I|dt
for one time period T.
V_C = 1/C | dt
where, T = 1/f = 2 ms
3 = 1/ 2 uF |^2X10 I dt
I = 3 mA
The charging requires constant current source of 3 mA for 2 m.

55. (c)

Slew rate = A x 2 V_m
V = AV _m sin ₀₀t
dV/dt = A V_{M 00} cos ₀₀t
dV/ dt |_max SR = AV_M 2 fm
= 20 log x = 40
x = 100 =  A
V_M = SR / A x 2 fm = 1/ 10^-6 x 100 x 2_z x 20 x 10³
V_M = 79.5 mV

56. (a)

applying KVL at node 1,
BV_O – 0 /R₁ + BV_O x V_O /R₂ = 0
B (1/R₁ + 1/R₂) = 1/R₂
B x R₁ + R₂/R₁ = 1
R₁ (1 + R₂/R₁) = 1/B = 6
R₂/R₁ = 5
R₂ = 5R₁

57. (a)

V_IN – V_O/R > I_Z + I_L (I₁)
I_Z + I_L = I₁, when V₁= 30 V
30 – 10 /R > (10 + 1) mA = 20/R > 11mA
R < 1818, When V_IN = 50 V
40/R > 11 x 10^-3
R > 3636, from this R < 1818

58. (d)

g_m = 2 I_DSS/V_D (1 – V_GS/V_D)
V_G = 0, V_S = I_D R_S
= 1 mA x 2.5  k = 2.5 V
V_GS = V_G – V_S = – 2.5 V
g_m = 2 x 10 /5 mA [1 – (-2.5/-5)] = 2 mS
A_V = – g_mR_D
= – 2 mA x 3 k = – 6

59. (c)

F_T = g_m/2 (c_u + 2)
putting the value F_T = 1.47 x 10¹⁰ Hz
from the relation
f_b h_fe < f_t
f_b = f_t/h_fe
putting the vlue
F_B = 1.64 x 10⁸ Hz

60. (c)

we can write
I_E = I_C + I_Z
I_B < I_Z
I_C/I_B = 99
Hence,   I_E = 100 I_Z
From the circuit we can write
I_Z = 1/100 = 0.01 A
I_C = 99I_Z = 0.99 A
P_Z = V_ZI_Z = 9.5 x 0.01 mW
p_t = V_CI_C = 10 x 0.99 = 9.9 w

61. (a)

the tank circuit indicated in figure has capacitor divided cicuit with inductor in paraller, hence it is a colpitts oscillator.
C_eq = C₁C₂/C₁ + C₂ = 1 pF
f = 1/2 LC_eq = 79.6 MHz

62. (d)

Let A_ol be open-loop gain
V_O = A_OL V_L ………………………(1)
Applying KCL at node A,
V_S – V_I/R₁ = V_I – V_O/R₂
Putting the value of V_I from eq. (1)
V_S – V_O|A_OL/R₁ = V_O|A_OL – V₀/R₂
V_S = -89/1000 V_O
A_CL = V_O/V_S = – 1000/89 = – 11

63. (a)

0p-amp (1) circuit works as differentiator with time constant.
L /R = 10 x 10^-3/10 = 10^-3s
op-amp (2) circuit works as integrator with time constant.
RC = 10^-3s
hence the final output will be same as input 10 cos (100 t )

64. (d)

V_IN = R_L/R₁ + R₂ x V_CC = 5/15 x 15 = 5 V
since, B is large I_B = 0, R_in = 5||10
I_C = V_IN – V /R_C = 5 – 0.7 /430 K = 4.3 /0.430 K
= 10 mA

As no input voltage applied and op-amp has V_IN (offset) = 5 mV
V_O (offset) = A_O < V_IN (offset)
= 5 mV x 10,000
= 50 V
V_O > V_sat
hence, op-amp is in saturation. hence, output voltage is + 50 mV.

66. (d) CMRR for the differential amplifier will be

node (1) V_A – V₁/1 + V_A – V₀/90 = 0
91V_A = V_O + 90V₁
Node (2) V_A/100 + V_A – V₂/1 = 0
10IV_A – 100V₂ = 100 x 0
101V_A = 100V₂
V_A = 100V₂/101
91 x 100V₂/101 = V₀ + 90V₁
V_O = 91 x 100/101 V₂ – 90V₁
V₁ = V_C + V_D/2 and V₂ = V_C – V_D/2
V_O = 9100/101 (V_C – V_D/2) – 90 (V_C + V_D/ 2)
V_O = 9100/101 V_O/2 – 9100/101 V_D/2 – 90V_C/2 – 90V_D/2
= 0.099 V_C/2 – 90.04 V_D
= 0.0495V_C – 90.04 V_D
A_D = 90.04
A_C = 0.0495

67. (a)

common base amplifier has low input inpedance and low current gain.

68. (a)

I_DSS = 10 mA, V_P = 5 V
I_D = 6.4 mA
I_D = I_DSS (1 – V_GS/V_P)²
6.4/10 = (1 – V_GS/V_P)
0.2 V_P = V_GS
V_GS = 1V
V_GS = I_DR_S
R_S = 1/6.4 x 10^-3
R_S = 156.25
R_S = 150

69. (c)

for class-A n= 50 %
P_max > P_AC x 100 /n = 10 X 100/50 = 20 W

70. (b)

thermal resistance 0_j = T_max – T_A/P = 125 – 25/100mW
= 1000⁰ C/W
The thermal resistance obtained is very high because it is obtained without use of any heat sink.

71. (a)

A_F = A_OL/1 + A_OLB = 100/1 + 100 x 0.99 = 1
f_h = f_h(1 + BA_OL)
= 100 x 10³(1 + 0.99 x 100) = 10 MHz

72. (d)
73. (c)

power delivered.
P_D = 50 x 50/100 = 25 w
p_d = T_I = T_A/0_JE
0_JE = 150 – 25/25 = 5⁰ C/W

74. (b)

change in value of R_E in differential amplier affects the common mode gain A_C.

75. (b)

For current -series to pology
Z_IF = Z_I (1 + BA)
Z_OF = Z_O (1 + BA)

76. (c)

common emitter short cicuit current gain B of a transistor increases with I_C when I_C reaches a maximum value then B decreases with further increase in I_C

77. (b)
78. (c)

In common emitter BJT amplifer maximum usable, supply voltage is limited by collector emitter breakdown voltage with base open (BV_CBO).

79. (a)

In cascade amplifier, CE followed by CB.

80. (b)

Given circuit is common emitter circuit in AC analysis, capacitance acorss RE mode
RE = 0
So, RE will not come in AC analysis and gain (voltage gain) increases, but input impedance.
if RE (emitter resistance) present , it will always reduce the gain.

81. (a)
82. (b)

input impedance decreases and output impedance increases in short-shunt negatvie feedback. it is also called as voltage shunt feedback.

83. (b)
84. (a)
85. (d)
86. (a)

from figure, V₁/V₂ = R_D/2_/R_D = 1/2
V₁ = V₂/2

87. (c)

Two identical resistances in parallel give equivalent value that is half of the individual resistance value , i.e., r_d/2 and two identical transconducances in parallel get added
equivalent transconductance is 2 g_m

88. (a)
89. (a)

g_m = I_O/V_I , I_O = I_E2 = I_C1
I_C1 = BI_B1, I_E2 = I_C2
I_O = BI_B1 , V_I = I_B1 r
I_O/V_I = BI_B1/I_B1r
= g_m1 = I_C1/V_I                (as I_C1 = BI_B1)

90. (b)

In class-B crossover distortion is produced in output waveform.

91. (a)

f_t = 1/2 RC
1/R = g_m I_C/V_T
f_t = I_C/2 V_T x C_U
C_U = 1 mA/2 x 26 mV x 400 x 10⁶
C_U = 15 pF

92. (c)

open -loop gain = 100
B = 0.99
Input impedance = 1 k
output impedance = 100 k
voltage series feedback
Z_IF = Z_I (1 + AB)
= 1 x 10³ (1 + 100 x 0.99)
Z_IF = 100 K
Z_IF = Z_O/1 + AB
Z_OF = 100/1 + 100 x 0.99)
Z_OF = 1

93. (b)

amplifier has a single pole high frequency transfer function.
rise time to a step function = 35 n
t_r x B ₀₀ = 0.35
B ₀₀ = 0.35/35 x 10^-9 = 10 MHz

94. (c)

The given circuit work as logarithmic amplifier

95. (a)

I₁ = I₂ = 2 mA
Applying KCL at A.
I₂ + I_X = I_L
2 + I_X = V_O/R_L
I_L = V_O/R_L
V_O = – 2 K x – 2 mA = – V
I₂ = – 4 /2 = – 2 mA
2 + I_X = – 2
I_X = – 4 mA