For good stabilized biasing of the transistor of CE amplifier of figure, we should have

Unit Exercise-2
(2 Marks questions)

1. Consider the circuit shown in figure below, if the diode used here has the V-I characteristic as in figure below, then the output waveform V_o is
2. The rms value of a rectangular wave of period T, having a value of + V for a duartion T, (<T) and having -V for the duration, T – T₁ = T₂ equals

(a) V
(b) T₁ – T₂/ T  V
(c) V /2
(d) T₁/T₂ V

3. For good stabilized biasing of the transistor of CE amplifier of figure, we should have

(a) R_E/R_B <<1
(b) R_E/R_B >>1
(c) R_B/R_E <<1
(d) R_B/R_E <<1

4. Discrete transistors T₁ and T₂ having maximum collector current rating of 0.75 A, are connected in paraller as shown in the figure. this combination is treated as a single transistor to carry a total current of 1 A, when biased with self bias circuit. when the circuit is switched on, T₁ draws 0.55 A and T₂ draws 0.45 A. if the supply is kept on continuously, ultimately it is very likely that

(a) both T₁ and T₂ get dmage
(b) both T₁ and T₂ will be safe
(c) T₁ will get damage and T₂ will be safe
(d) T₂ will get damage and T₁ will be safe

5. The secondary transformer voltage of the rectifier circuit shown below is V_S = 60 sin 2 60_t V. each diode has a cut-in voltage V_in = 0.6 V the ripple voltage is to be no more than V_rip = 2V. The value of filter capacitor will be

(a) 48.8 uF
(b) 24.4 uF
(c) 32.2 uF
(d) 16.1 uF

6. The input to full-wave rectifier shown below is V_I = 120 sin 2 60_t V. The diode cut-in voltage is 0.7 V. if the output voltage cannot drop below 100 V, the required value of the capacitor is

(a) 61.2 uF
(b) 41.2 uF
(c) 20.6 uF
(d) 30.6 uF

7. For the circuit shown below, diode cut-in voltage is V_in = 0. the ripple voltage is to be no more than V_RIP = 4 V. the minimum load resistance, that can be connected to the output is

(a) 6.25 k
(b) 12.50 k
(c) 30 k
(d) none of these

8. The JFET in the circuit shown in figure below has an I_DSS = 10 mA and V_P = 5 V. The value of the resistance R_S for a drain current I_DS = 6.4 mA is

(a) 150
(b) 470
(c) 510
(d) 1 k

9. In a transistor push-pull amplifier

(a) there is no DC present in the output
(b) there is no distortion in the output
(c) there are no even harmonics in the output
(d) there are no odd harmonics in the output

10. In a multistage RC copled amplifier, the coupling capacitor

(a) limites the low frequency response
(b) limits the high frequency response
(c) dose not affect the frequency response
(d) blocks the DC component without affecting the frequency of response

11. Negative feedback in amplifiers

(a) improves the signal to noise ratio at the input
(b) improves the signal to noise ratio at the output
(c) does not affect the signal to noise ration at the output
(d) reduces distortion

12. The bandwidth of an n stage tuned amplifier with each state having a bandwidth of B, is given by

(a) B/ n
(b) B/n
(c) B  2^1/n -1
(d) B / 2^1/N – 1

13. An n-p-n transistor has a beta cut-off frequency f_b of 1 MHz, and common-emitter short circuit low frequency current gain B₀ of 200. if unity gain frequency f_r and the alpha cut-off frequency f_a respectively, are

(a) 200 MHz, 201 MHz
(b) 200 MHZ, 199 MHz,
(c) 199 MHz, 200 MHz
(d) 201 MHz, 200 MHz,
14, The transfer characteristic for the precision rectifier circuit shown below is (assume ideal op-amp and practical diodes)

15. In the circuit below, the diode is ideal. the voltage V is given by

(a) min (V_I,1)
(b) max (V_I,1)
(c) min (-V_i,1)
(d) max (-V_I,1)

16. in the following astable multi-vibrator circuit, which properties of V_a (t) depend on R₂?

(a) only the frequency
(b) only the amplitude
(c) both the amplitude and the frequency
(d) neither the amplitude nor the frequency

17. A small signal source V_I(t) = A cos 20t + B sin 10⁶ t is applied to a transistor amplifier as shown below. the transistor has B = 150 and h_ie = 3 k which expression best approximates V_O (t) ?

(a) V_O (t) = – 1500 (A cos 20t + B sin 10⁶ t)
(b) V_O (t) = – 150 (A cos 20t + B sin 10⁶ t)
(c) V_O (t) = – 1500 B sin 10⁶ t
(d) V_O (t) = – 150 B sin 10⁶ t

18. For the circuit shown in the following figure, transistors M₁ and M₂ are identical n-MOS transistors. assume that M₂ is in saturation and the output is unloaded.

The current I_G is related to I_blas as
(a) I_x  = I_bias + I_S
(b) I_x  = I_bias
(c) I_x = I_bias – I_S
(d) I_x = I_bias – (V_{CC –} V_OUT/R_E)

19. The measured transconductance g_m of an n- MOS transistor operating in the linear region is plotted against the gate voltage V_G at constant drain voltage V_D which of the following figures represents the expected dependence of g_m on V_G?
20. Consider the following circuit using an ideal op-amp. the I – V, characteristics of the diode is described by the relation I = I_O (e^v/v_t – 1) where V_T = 25 mV, I_O = 1 uA and V is the voltage across the diode (taken as positive for forward bias)

For an input voltage V_I = – 1V, the output voltage V_O is
(a) zero
(b) 0.1 v
(c) 0.7 v
(d) 1.1 v

21. The op-amp circuit shown below represents a

(a) high – pass filter
(b) low-pass filter
(c) band-pass filter
(d) band-reject filter

22. Two identical n-MOS transistors M₁ and M₂ are connected as shown below. V_bias is chosen, so that both transistors are in saturation. the equivalent g_m of the pair is defined to be I_OUT/V_I at constant V_OUT.

The equivalent g_m of the pair is
(a) the sum of individual g_m‘s of the transistors
(b) the product of individual g_m‘s of the transistors
(c) nearly equal to the g_m of M₁
(d) nearly equal to g_m/g_o of M₂

23. An astable multi-vibrator circuit using IC 555 timer is shown below in figure, assume that the circuit is oscillating steadily.

The voltage V_C across the capacitor varies between
(a) 3 v to 5 v
(b) 3 v to 6 v
(c) 3.6 v to 6 v
(d) 3.6 v to 5 v

24. Consider the schmitt trigger circuit shown below. A triangular wave which goes from -12 v to 12 v is applied to the inverting input of the op-amp. assume that the output of the op-amp sings from + 15 v to – 15 v. the voltage at the non-inverting input switches between

(a) – 12 v and + 12 v
(b) – 7.5 v and + 7.5 v
(c) – 5 and + 5 v
(d) 0 v and 5 v

25. For the op-amp circuit shown in the figure below, V_O is

(a) – 2 v
(b) -1 v
(c) – 0.5 v
(d) 0.5 v

26. For the BJT circuit shown in figure below, assume that the B of the transistor is very large and V_BE = 0.7. the mode of operation of the BJT is

(a) cut-off
(b) saturation
(c) normal active
(d) reverse active

27. In the op-amp circuit shown in figure below assume that the diode current follows the equation I = I_S exp (V/V_T) for V_I = 2V, V_O = V_O1 and for V_I = 4 V, V_O = V_O2. the relationship between V_O1 and V_O2 is

(a) V_O2 = 2 V_O1
(b) V_O2 E²V_O1
(c) V_O2 = V_O1 in 2
(d) V_O1 – V_O2 = V_T In 2

28. In the CMOS inverter circuit shown in figure below, if the transconductance parameters of the n-MOS and p-MOS transistors are

K_n = K_p = u_n C_ox W_n/L_n = u_p C_ox W_p /L_p = 40 u/A/V² and their threshold voltages are V_TH,_N =|V_{th, p}| = 1V, the current / is
(a) zero
(b) 25 uA
(c) 45 uA
(d) 90 uA

29. For the zener diode shown in the figure below, the zener voltage at knee is 7 V, the knee current is negligible and the zener dynamic resistance is 10 if the input voltage (v_i) range is from 10 to 16 v, the output voltage (V_O) ranges from

(a) 7.00 V to 7.29 V
(b) 7.14 V to 7. 29 V
(c) 7.14 V to 7.43 V
(d) 7.29 V to 7.43 V

30. For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0, the switch S is closed. the voltage V_C across the capacitor a t = 1 ms is

(in the figure shown above, the op-amp is supplied with + 15 V and the ground has been shown by the symbol v).
(a) zero
(b) 6.3 v
(c) 9.45 v
(d) 10 v

31. For the circuit shown below, assume that the zener diode is ideal with a breakdown voltage of 6 v. the waveform observed across R is
32. For an n-p-n transistor connected as shown in figure below, V_be = 0.7 v. given that reverse saturation current of the junction at room temperture 300 k is 10^-13 A, the emitter current is

(a) 30 mA
(b) 39 mA
(c) 49 mA
(d) 20 mA

33. The voltage V_O indicated in figure below has been measured by an ideal voltmeter. which of the following can be calculated?

(a) bias current of the invertnig input only
(b) bias current of the inverting and non-inverting inputs
(c) input offset current only
(d) both the bias current and the input offset current

34. The op-amp circuit shown in figure below is a filter. the type of filter and its cut-off frequency are respectively

(a) high-pass, 1000 rad/s
(b) low-pass, 1000 rad/s
(c) high-pass, 1000 rad/s
(d) low-pass, 1000 rad/s

35. In an ideal differential amplifer shown in figure below, a large value of R_B

(a) increases both the differential and common mode gains
(b) increases the common mode gain only
(c) decreases the differential mode gain only
(d) decreases the common mode gain only

36. For an n-channel MOSFET and its transfer curve shown in figure below, the threshold voltage is

(a) 1 v and the device is in active region
(b) -1 v and the device is in saturation region
(c) 1 v and the device is in saturation region
(d) – 1 v and the device is in active region

37. The circuit using a BJT with B = 50 and V_BE = 0.7 v shown in figure. the base current I_b and collector voltage V_c are, respectively

(a) 43 uA and 11.4 V
(b) 40 uA and 16 V
(c) 45 uA and 11 V
(d) 50 uA and 10 V

38. The zener diode in the regulator circuit shown in figure has a zener voltage of 5.8 v and a zener knee current of 0.5 mA. the maximum load current drawn from this circuit ensuring proper functioning over the input voltage range between 20 and 30 v, is

(a) 23.7 mA
(b) 14.2 mA
(c) 13.7 mA
(d) 24.2 mA

39. Given, the ideal operational amplifier circuit shown in figure indicates the correct transfer characteristics assuming ideal diode with zero cut-in voltage.
40. The drain of an n-channel MOsfet is shorted to the gate, so that v_gs = V_ds the threshold voltage (V_T) of MOSFET is 1 V. if the drain current (I_d) is 1 mA for V_gs = 2 V, then for V_gs = 3 V, I_D is

(a) 2 mA
(b) 3 mA
(c) 9 mA
(d) 4 mA

41. Assuming that the B of the transistor is extremely large and V_BE = 0.7 V, I_C and V_CE in the circuit shown in figure, are

(a) I_C = 1 mA, V_CE = 4.7 V
(b) I_C = 0.5 mA, V_CE = 3.75 V
(c) I_C = 1 mA , V_CE = 2.5 V
(d) I_C = 0.5 mA, V_CE = 3.9 V

42. A bipolar transistor is operating in the active region with a collector current of 1 mA. assuming that the B of the transistor is 100 and the thermal voltage (V_T) is 25 mV, the transconductance (g_m) and the input resistance (r_i) of the transistor in the common emitter configuration are

(a) g_m = 25 mA/V and r_i = 15.625 k
(b) g_m = 40 mA/ V and r_i = 4.0 k
(c) g_m = 25 mA/ V and r_i = 2.5 k
(d) g_m = 40 mA/ V and r_i = 2.5 k

43. The value of c required for sinusoidal oscillations of frequency 1 kHz in the given circuit, is

(a) 1/2 uF
(b) 2 uF
(c) 1/2 6uF
(d) 2/6 uF

44. In the op-amp circuit given in figure the load current I_L is

(a) – V_S/R₂
(b) V_S/R₂
(c) -V_S/R_L
(d) V_S/R_L
answer key with solution 

1. (c) V_L < 0.5 V, V_O = 0

V_L > 0.5 V, V_O = 600 /600 + 300 (V_L – 0.5)
V_O – 2/3 (V_L – 0.5)

2. (a)
3. (b) For biasing stability R₁||R₂ = R_B

S = R_B/R_E >>> (B + 1)
S = B + 1
For R_B/R_E >>> 1, then
S = B + 1 ( 1/B + 1) = 1
Here, R_B/R_E << 1, So, R_E/R_B >> 1

4. (c) T₁T₂ draw total current = 1 amp

when on, T₁ draws 0.55 A
T₂ draws 0.45 A
T₁ is heated more than T₂
Finally, I₁ = 1A, I₂ = 0
T₁ is demaged, T₂ safe.

5. (b) V_S = 60 sin 2 60t V

V_max = 60 – 1.4 = 58.6 V
C = V_max/2fRV_rip = 58.6 / 2(60)10 x 10³ x 2 = 24.4 uF

6. (c) Full wave rectifier

V_S = V_t = 120 sin 2 60t V
V_max = 120 – 0.7 = 119.3 V
V_rip = 119.3 -100 = 19.3 V
C = V_max/2fkV_rip = 119.3 /2(60)2.5 x 10³ x 14.4 = 20.6 uF

7. (a) V_rip = V_max/fR_LC

R_L = V_MAX/fCV_rip = 60 x 50 x 10^-5 x 4 = 6.25 k

8. (a) I_D = I_DSS [1 – V_GS/V_P]²

6.4/10 = [1 – V_GS/V_P]² = 0.8 – 1 = – V_GS/V_P
0.2V_P = V_GS = V_GS = 1 V = V_GS = I_DR_S
R_S = 1/ 6.4 x 10^-3
R_S = 156.25
R_S = 150

9. (a,c) In transistor push-pull amplifier, there is no DC present. in output also, there are no even harmonics in output.
10. (a,d) coupling capacitor limits the low frequency response as well as blocks DC components.
11. (b,d) Negative feedback improves signal to noise ratio at output and reduces distortion.
12. (c) Bandwidth of n-stage tuned amplifier with each stage having BW of B is given by

B 2^1/n – 1

13. (a) f_t = B_OF_B = 200 x 1 MHz = 200 MHz

f_a = f_b/1 – a
f_a = f_b = f_b/1 (1 + B) = 1 x 10⁶ x 201
1 – B/1 + B
f_a = 201 MHz

14. (a)

This is an example of control precision. for V_I > – 5, diode D₂ Conducts and closes the negative feedback loop around the op-amp. a virtual ground therefore will appear at the inverting input termial and the op-amp output will be damped at one diode drop below ground. this negative voltage will keep the diode D₁ off, and no current will flow in the feedback resistanece R₂ that is, the rectifier output will be zero.
As V_I goes negative the voltage at the inverting input terminal will tend to go negative, causing the voltage at the op-amp output terminal to go to positive. this will cause D₂ to be reverse biased and bence cut-off. the current through the feedback resistance R₂ will be equal to the current through the input resistance R₁ For R₁ = R₂ the output voltage
V_O = – V_I – 5 for V_I < – 5 V
Hence, transfer characteristics will be

15. (a)

For V_I > 1 V, the diode is reverse biased and V = 1 V.
For V_I < 1 V, the diode is forward biased and V = V_I.
Hence, V = min (V_I, 1)

16. (a)

The output amplitude
V_O = R₄/R₄ + R₃(+ V_sat)
the output frequency f = 1/ 2R₂C
Hence, only frequency of V_O depends on R₂

17. (b)

The output voltage
V_O – h_feRC/h_ie V_I
V_O – B R_C/h_ie V_I
V_O – -150 x 3 x 10³/3 x 10³ V_I
V_O – 150 V_I
V_O – 150 (A cos 20 t + B sin 10⁶ t)

18. (b)

the circuit acts as current mirror.
I_x = (₀₀/L)₂ / (₀₀ /L)₁ I_bias
since, both the MOSFETs are identical.
(₀₀/L)₂ = (₀₀/L)₁
Hence, I_x = I_bias

19. (c)

We know that I_D = K (V_GS – V_T)²
The transconductance
g_m = I_D/V_GS
g_m = 2k (V_GS – V_T)
Hence, g_m varies linearly with V_GS.

20. (b)

From virtual ground concept the potential of A, V_A = 0. Let the diode conduct, and current flows as indicated in figure.
I = 0 – (-1) /100 K
I = 1 / 100 K
Given,  I_O = I_O (e^v/vt – 1)
1/100 k = 1uA (e^{vo/25 mV} -1)
1/ 100 x 10³ x 1 x 10^-6 = (e^{vo/25 mv} – 1)
10 + 1 = 1 = e^{vo/25 mv}
V_O = 0.1 V

21. (b)

V_O = – Z₂/Z₁ V_I
Z₂ = R₂ x 1/SC = R₂/1 + sR₂C
R₂ + 1/SC
Z₁ = R₁ + sL
V_O = R₂/ (1 + sR₂C) (R₁ + sL) V_I
V_O/V_I = s²R₂LC + s (L + R₁R₂C) + R₁
The standard form of low-pass filter
V_O/V₁ = K /as² + bs + c
hence, op-amp circuit represents low-pass filter.

22. (c)

The equivalent transconductance
g_m = g_m1g_m2/g_m2 + g_m1
g_m2 >> g_m1 ; because of V_bias
hence, dg_m – g_m1

23. (b)

the capacitor is periodically charged and discharged between 2/3 V_CC and 1/3 V_cc.
V_C varies between 1/3 x 9 and 2/3 x 9, i.e., between 3 and 6.

24. (d)

the circuit is let V_A be the voltage of non-inverting terminal.
applying KCL at node V_A, 1.5 – V_A/10 + V_O – V_A/10 + -15 – V_A/ 10 = 0
V_A = V_O/3
As the output of op-amp swings between – 15V to + 15 v. the voltage between the non-inverting input switches from – 5 to + 5 v.

25. (c)

V_A = 1/1 + 1 (1 V) = 0.5 V (From voltage divided rule)
applying KCL at node B,
1 – V_B/1 K = V_B – V_O/ 2 K
From virtual group concept,
V_B = V_A = 0.5 V
1 – 0.5 /1 K = 0.5 – V_O / 2 K
1 = 0.5 – V_O
V_O = – 0.5 V

26. (b)

Assuming BJT is in active region,
I_E = 2 – V_BE/R_E = 2 – 0.7 / 1 K = 1.3 mA
As B is large,
I_E = I_C = 1.3 mA
Applying KVL in collector emitter loop,
10 – 10I_E – V_CE – I_C = 0
V_CE = – 4.3 K
V_BC = V_BE – V_CE
= 0.7 – (- 4.3) = 5 V
Since, V_BC > 0.7 V
transistor in saturation.

27. (d)

V_I/R = I_D = I_S e^vd/vt
V_D = V_T IN V_I/I_SR
Given, when
V_I = 2 V
V_O = V_O1
0 – V₀₁ = V_T in 2/I_SR ……………..(i)
when V_I = 4 V
V₀ = V₀₂
0 – V₀₂ = V_T in 4/I_SR …………….(ii)
subtracting eq. (i) from eq. (ii)
V_O2 – V_O1 = V_T in 4/I_SR – V_T in 2/I_SR
= V_T in 4 /I_SR x I_SR/2 = V_T in 2

28. (d)

Given that
(V_T) _{p -MOS} = (V_T) _n-MOS = 1 v
k = (₀₀/L) _p-MOS = (₀₀/L) _n-MOS = 40 uA/V²
V_GS = 2.5 V
I_D = K (V_GS – V_T)²
= 40 uA/V² (2.5 – 1)²
I_D = 90 uA

29. (c)

when    V_I = 10 V
V_R = V_I – V_Z = 3V
R = 3/200 = 15 mA
V₀ = V_Z + I_R 10 = 7.15 V
When   V_I = 10V
V_R = 9V
I_R = 9/200 = 45 mA
V₀ = V_Z + 1_R x 10 = 7.45 V
Ouput range is 7.15 V – 7.45 V.

30. (d)

from concept of virtual ground, the potential at 1 is 10 v. appiying KCL at node 1,
0 – 10 /1 k = – c dv_c/dt
10 x 10^-3 = 1 x 10^-6 dv_c/dt
V_C = 10 x 10^-3/1 x 10^-6 | dt
= 10 x 10^-3/1 x 10^-6 x 1 x 10^-3 = 10 v

31. (a)

when 0 < v_i < 6V ;
Zener breakdown doesn’t occur and
V_R = 0
6V < V₁ < 12 V,
V_R = V_IN – 6

32. (c)

as collector and base are connected, hence, emitter base junction works as diode.
hence, from diode equation,
I_D = I_S (e_v/nvt – 1)
I_D = I_E
I_D = I_S (e_v/nvt – 1)
= 10 ^-13 (e^{0.7/1 x 26 x 10-3} – 1)
= 49 mA

33. (c)

The output voltage due to input bias current of inverting terminal is same and the output voltage due to input bias current of non-inverting terminal is same and of opposite sign as resistance is same at both ports.
(V_O)_offset = I_Off R₂
hence, by calculating V_O, we can measure input offset current only for given circuit.

34. (a)

let V_A be the input of non-inverting input
V_O = (1 + R_F/R₁) V_A
V_O = (1+1) V_A = 2V_A
= 2 x V₁ x R₂ = 2V₁R₂C_S/1 + sR₂C
R₂ + 1/SC
At DC (low frequency)
V_O = 0
At high frequency output is finite hence it is a high-pass filter.
As the pole exits at 1/R₂C.
hence, cut-off frequency
_00c = 1/R₂C = 1/1 x 10³ x 1 x 10^-6
= 1000 rad/s

35. (d)

In ideal differential amplifier.
common mode gain = – R_C/2R_E
Differential mode gain = – g_mR_C
(doesn’t depend on R_E)
Hence, by increasing R_E, the common mode gain will be decrease.

36. (c)

From graph threshold voltage V_T = 1V
V_DS = V_D – V_S = 5 – 1 = 4 V
V_GS = V_G – V_S = 3 -1 = 2 V
As    (V_DS) > (V_GS – V_T)
Hence, device is in saturation.

37. (b)

Applying KVL in collector base circuit,
V_CC – I_BR_B – V_BE – I_ER_E = 0
I_E = I_C + I_B
= BI_B + I_B = I_B (1 + B)
V_CC – I_BR_B – V_BE – I_B (1 + B) R_E = 0
I_B = V_CC – V_BE/(1 + B) R_E + R_B
= 40 uA
I_C = BI_B = 2 mA
collector voltage V_C = V_{CC –} I_CR_C
= 20 – 2 x 10^-3 x 2 x 10³
= 16 V

38. (a)

the maximum current theough load flow when there is maximum input voltage i.e., V_IN = 30 V.
Let I_E be knee current and I_L be load current at V_in = 30 V. Applying KVL,
30 – (I_L + I_Z) x 1 K – 5.8 = 0
= 24.2 mA
I_L = 24.2 mA – I_Z
Given,   I_Z = 0.5 mA
(I_L)_max = 24.2 – 0.5
= 23.7 mA

39. (b)

When V_IN < 0; V_O > 0,    D₂ conducts and D₁ does not conduct
V_U = 2 K/2.5 K V_sat
= 2 /2.5 x 10 = 8 V
when V_IN = 0, V_O < 0; D₁ conducts and D₂ is in cut-off
V_I = 2 K /2.5 K V_sat = 2/4 (-10) = – 5 V

40. (d)

We know that,
I_DS = I_DSS (1 – V_GS/V_T)²
1 = I_DSS (1 – 2/1)²
I_DSS = 1 mA
For     V_GS = 3 V
I_DS = I_DSS(1 – V_GS/V_T)² = 1 (1 – 3/1)² = 4 mA

41. (c)

Thevenin equivalent of circuit
where,   V_TH = 5 x( 1/1 + 4) = 1 V
R_Th = 4/5 k
applying KVL in base emitter loop,
V_TH – R_ThI_B – V_BE = I_ER_E
I_E – I_C
I_C = 1 mA
V_CE = 5 – I_CR_C – I_ER_C = 2.5 V

42. (d)

Transconductance
g_m = |I_C| /V_r = 1 mA /25 mV
= 0.04 A /V = 40 mA /V
= B = g_mr
= r = B/g_m = 100 /40 x 10^-3 = 2.5 k

43. (a)

The given circuit is wien bridge oscillator.
⁰⁰₀ = 1/RC
2f₀ = 1/RC
C = 1/2f₀R = 1/2 x 10³ x 10³
C = 1/2 uF

44. (a)

Applying KCL at node A,
V_S – V_A/R₁ = V_A – V_O/R₁
V_S – V_A = V_A – V_O
2V_A – V_O = V_A
V_A = (V_O + V_S) /2
Applying KCL at node B,
V_B/R₂ + I_L + V_B – V_O/R₂ = 0
From virtual ground concept,
V_A = V_B
2 (V_O + V_S) /2 – V_O + I_LR₂ = 0
I_L = – V_S/R₂