Determine the output voltage of an op-amp for input voltage of 200 uV and 160 uV. the differential gain of op-amp is 4000 and value of CMRR is 150

Intro Exercise-7

10. Determine the output voltage of an op-amp for input voltage of 200 uV and 160 uV. the differential gain of op-amp is 4000 and value of CMRR is 150.

(a) 16 V
(b) 164.8 mV
(c) 64 mV
(d) 76 mV
answer and solution :

10. (b) For CMRR of 150 and A_D = 4000

V_D = V₁ – V₂ = 200 – 160 = 40 uV
V_C = V₁ + V₂ / 2 = 200 + 160 /2 = 180 uV
V₀ = A_DV_D [1 + 1/CMRR V_C/V_D]
= 4000 x 40 x 10^-6 [1 + 1/150 180/40]
= 164.8 mV

1. For the circuit shown below the value of A_V = V_O /V_I is

(a) – 10
(b) 10
(c) -11
(d) 11

2. For the circuit shown below the value of A_V = V_O / V_I

(a) -10
(b) 10
(c) 13.46
(d) -13.46

3. For the circuit shown below the value of A_V = V₀ / V_i is

(a) 5
(b) -5
(c) 6
(d) -6

4. For the circuit shown below, the value of V_O is

(a) 4/3 V
(b) – 2/3 V
(c) 2/3 V
(d) – 4/3 V

5. For the circuit shown below the value of V_O is

(a) -30 V
(b) 18 V
(c) – 18 V
(d) 28 V

6. The expression for the output voltage V_O in terms of the input voltage V₁ and V₂ in the circuit shown below, assuming the operational amplifier to ideal is

The values of A₁ and A₂ would be respectively
(a) -9 and 10
(b) 9.9 and -10
(c) 9 and – 10
(d) -9.9 and 10

7. For the following circuit, the gain will be

(a) 5.92
(b) 2.82
(c) 4.67
(d) 1.93

8. In the circuit given below, the CMRR of the op-amp is 30 dB. the magnitude of the V_O is

(a) 2 mV
(b) 100 mV
(c) 200 mV
(d) 1 mV

9. The output voltage produced by cascaded integrators at t = 0.5 s

(a) 6 V
(b) 4 V
(c) 3 V
(d) 10 V
 

11. In the op-amp circuit shown below, it is desired that V₀ = V₂/3 – 2V_1, what is the value of R to achieve V₀ ?

(a) 100 k
(b) 40 k
(c) 80 k
(d) 30 k

12. The gain of following circuit is

(a) R₂/R₁ (V₂ – V₁)
(b) R₁/R₂ (V₁ – V₂)
(c) R₁/R₂ (V₂ – V₁)
(d) R₂/R₁ (V₁ -V₂)

13. The input voltage in shown below circuit is V_I = 5 sin _00t mV. the current I_O is

(a) -2 sin ₀₀t uA
(b) -2.2 sin ₀₀t uA
(c) -5 sin ₀₀t uA
(d) Zero
Statement for linked answer questions 14 and 15
consider the following circuit :

14. The output voltage V₀ is

(a) -12 V
(b) 12 V
(c) -18 V
(d) 18 V

15. Input impedance seen by the voltage source is

(a) 5 k
(b) 6/5 k
(c) 6 k
(d) ₀₀

16. In the folllowing amplifier circuit the op-amp is ideal the voltage V_B is

(a) zero
(b) – 1.2 v
(c) – 3 v
(d) 2.1 v

17. An audio amplifier is designed to have a small-signal bendwidth of 20 kHz. the open – loop low-frequency voltage gain of the op-amp is 10⁵ and unity gain bandwidth is 1 MHz. what is the maximum closed-loop voltage gain for this amplifier ?

(a) 500
(b) 5 x 10⁶
(c) 2 x 10⁶
(d) 50
Answers With Solutions

1. (a) This circuit is inverting amplifier.

We know A_V = gain = R_F / R₁ = 400/40 = – 10

2. (a) The non-inverting terminal (B) is at ground level. thus inverting terminal ia also at virtual ground. there will not be any current in 60 k.

Gain = A_V = – 400/40 = – 10

3. (a) The circuit is as follows

V_O = V_I = V_B
Let V_I the node voltage of T network.
V_B/R + V_B – V₁ / R = 0
V₁ = 2V_B = 2V_I
V₁ – V_B / R + V₁ /R + V₁ – V_O /R = 0
3V₁ = V_B + V_O
6V₁ = V_I + V₀
V₀ /V_I = 5

4. (a) The circuit is as follows

V_a = 6 x 6 / 48 + 6 = 2/3 V
V_a = (1 + 10/10) V_a = 4/3 V

5. (a) The circuit is as follows

V₁ = V_O(4) / 4 + 8 + 12(8) /4 + 8
V_a = – 2 V, V_a = V_b
V_O /3 + 8 = – 2, V_O = – 30 V

6. (b) V_B = V₁ – V₁ / 110 x 11 = 0.9 V₁

V_A = V_B = 0.9 V₁
Again   V₀ – V_A / 100 = V_A – V₂ /10
Or     V_O – 0.9 V₁ /100 = 0.9V₁ – V₁ /10
Or       V₀ = 9.9V₁ – 10V₂
Here,   A₁ = 9.9 and A₂ = – 10

7. (c) Gain of instrumentation amplifier is

A = R₄ / R₃ [1 + 2R₁ / R₂]
= 5.6/3.2 [1 + 2 x 4.7 / 5.6] = 1.75 (2.67)
= 4.67

8. (b) V_a = 2 R/2R = 1 V

V_B = 2 R/2R = 1 V
V_D = V_A – V_B        V_D = 0
V_CM = V_A + V_B / 2 = 1
V₀ = R_FV_CM / 1 CMRR
CMRR = 60 dB = 10³
V_O = 100/1 1/10³ = 100 mV

9. (d) V₁ = V_INT/RC = 0.1_TV_S / 0.025

V₁ = 4_T V_at t = 0.5
= – 4 x 0.5 = – 2 V
V₂ = – V₁t / 2RC = – 4t²/ 2RC = 4t² / 0.1s V
At  t = 0.5 s
V₂ = 4V x 0.5²/0.1 = 1/0.1 = 10 V
 

11. (c) V_O1 = – R_F / R₁ V₁ = – 2V₁

V₀₂ = [1 + R_F /R₁]V_B
= [1 + 10 /5] x V_B = 3V_B
V_B = V₂ /(R + 10) x 10;  V₀₂ = 30V₂ /(R + 10)
V₀ = V₀₁ + V₀₂ = – 2V₁ + 30V₂ /(R + 10)
As given V_O = V₂ /3 – 2V₁
– 2V₁ + 30V₂ / R + 10 = V₂/3 – 2V₁
R = 80 K

12. (a) Applying KCL at A, we get

V_X – V₁ /R₁ + V_X – V/ R₂ = 0
V_X [R₁ + R₂ /R₁R₂] – V₁ /R₁ = V/R₂ …………………(1)
At B, we get   V_X – V₂ /R₁ + V_X/R₂ = 0
V_X [1/R₁ + 1/R₂] = V₂/R₁ ………………(2)
Thus, from eqs. (1) and (2), we get
V₂/R₁ – V₁/R₁ = V/R₂
V = R₂/R₁ (V₂ – V₁)

13. (b) We know, V_A = – 15/5 (2 sin ₀₀t) mV = – 6 sin ₀₀t mV

Given,           A_V = r_o/r_i = – R_F/R₁
I₁ = V₀/5 = – 1.2 sin ₀₀t uA
I₁ = I₁ 5sin ₀₀t mV / 5 = 1 sin ₀₀t uA
I_e = I_L – I₁ = – 1.2 sin ₀₀t – sin ₀₀t
= – 2.2 sin ₀₀t uA

14. (a) The circuit is given by

Applying KVL to loop,
12 = 3 k I₁ + 2K I₁      I₁ = 2.4 mA
I₀ = I₁ = 2.4 mA
I₂ = – I₂ = – 2.4 mA
V₀ = I₂ (1K) = -2.4 V
V₀ = V_A – I_O(4K)
= – 24 – (2.4) (4) = – 12 V

15. (a) Input impedance is given by R_IN = V_S/I_S

Applying KVL to input loop
V_S – 3I₁ – 0 – 2I₁ = 0
R_IN = V_S/I₁ = 5 K

16. (b) Output voltage V_O is

V_O = V_S (R₂/R₁) = (-3) (-6.2 /1) = 18.6 V
V₀ > 10 V,
So,  V_O saturates at V₀ = + 10 V
By writing node equation at inverting terminal
V_B – (-3) /1 + V_B – (10) / 6.2 = 0
V_B [7.2/6.2] = – 3 + 10 /6.2
V_B = – 3 (6.2/7.2) + 10/7.2 = – 1.2 V

17. (d) Bode plot for the frequency response of op-amp is given by

here, f_cl x |A_CL|_MASS = F_U x 1
f_cl = close loop bandwidth
f_u = unity gain bandwidth
|A_CL|_MAX = maximum closed loop gain
(20 x 10³|A_CL|_MAX = 1 x 10⁶
|A_CL|_max = 50