Binary to BCD Converter | 8-bit binary to bcd converter circuit ic | step by step explanation

8-bit binary to bcd converter circuit ic | step by step explanation Binary to BCD Converter .

1. Binary to BCD Converter

This code converter combinational circuit is designed to convert binary to BCD code.

2. BCD to Excess-3 Code

Excess-3 code is modified BCD code. the combinational circuit convert BCD code into excess-3 code.
Truth table
In BCD to excess-3 truth table the unused codes are 1010, 1011, 1100, 1101, 1110 and 1111. so, place x (Don’t care) corresponding to these cells.

3. Excess-3 Code to BCD Code Converter

This circuit is designed to convert excess-3 code to BCD code.
Decoders
A decoders is a combinational logic circuit that converts binary information from n input lines to 2ⁿ unique output lines.
The decoder presented are called n-to-m line decoders, where m 2ⁿ.
Three to Eight Decoder
In 3 to 8 decoder, the three inputs are decoded into eight outputs, each representing one of the minterms of the three input variable.
Logic Diagram
Decoders include one or more enable inputs to control the circuit operation. A two-to-four line decoder with an enable input constructed with NAND gates is shown below.
Expanding Decoder
Decoder with enable inputs can be connected together to form a larger size of decoder circuit.
Figure shows two, 3 to 8 line decoder with enable inputs connected to form a 4 to 16 line decoder.
Example 1. Implement the following functions using decoder and gates
F₁ (A, B, C) = (0, 1, 3, 7)
F₂ (A, B, C) = (2, 3, 7)
Sol. Given minterm is function of three variables so, 3 to 8 decoder is required to implement the above function. the OR gate is used for separate output because the given expression in form of sum of product.
Encoder
An encoder is a combinational circuit that converts information into coded form. it has 2ⁿ (or fewer) input lines and n output lines.
Example 2. Desigs an octal to binary code converter.
Sol.  The octal to binary encoder has eight inputs and three outputs. in encoders it is assumed that only one input has a value of 1 at any given time.
Multiplexer
This is a combinational circuit that selects binary information from one of many input lines set of selection lines. there are 2ⁿ input lines and n selection lines whose bit combination determine which input is to be selected.
4 x 1 Multiplexer
In 4 x 1 multiplexer 4 represents number of inputs and 1 represents output line. so two select lines are required to select one of the inputs.
Logic symbol 4 to 1 Multiplexer
The boolean function of 4 to 1 multiplexer is written as follows :
Y = I₀S₁S₀ + I₁S₁S₀ + I₂S₁S₀ + I₃S₁S₀
Implementation of Boolean Expression Using MUX
The boolean function may be implemented in 2ⁿ to 1 multiplexer. the multiplexer inputs are n-1 variables, if we have a boolean function of n variables.
Example 3. Implement the following boolean expression using 8 x 1 MUX.
F (A, B, C, D)  = m (0, 2, 4, 6, 7, 9, 10)
Sol. Total number of variables = A, B, C, D = 4
Select line variable (2³) = 3 (B, C, D)
Input variable = 1 (A)
Now, we prepate the implementation table using the input variable and encircle the minterms 0, 2, 4, 6, 7, 9, 10 in the implementation table.
. If the two minterms in a column are encircled then 1 is placed to the corres ponding multiplexer inputs.
. If the two minterms in a column are not encircled, the 0 is placed to the corresponding multiplex input.
. If the minterms i firt row or second row is encircled (only one row is encircled not other) then apply the encircle row of variable to the corresponding multiplexer inputs.
Thus the logic diagram of given boolean expression
Example 4.  Implement the following boolean function
F (A, B, C, D) = (0, 1, 4, 6, 7, 9, 11, 15)
Using
(a) 8 x 1 MUX
(b) 4 x 1 MUX
(c) 2 x 1 MUX
Sol.  (a) 8 x 1 MUX
F (A, B, C, D) = (0, 1, 4, 6, 7, 11, 15)
Total number of variables = 4 (A, B, C, D)
Select line = 3 (B, C, D)
Input = 1 (A)
Logic Diagram
(b) Using 4 x 1 MUX
Total number of variables = 4 (A, B, C, D)
Select line = 2 (C, D)
Input = 2 (A, B)
Implementation Table
I₀ = AB + AB = A (B + B) = A
I₁ = AB + AB = B (A + A) = B
I₂ = AB
I₃ = AB + AB + AB
= AB + A(B + B) = AB + A
Logic Diagram
(c) 2 x 1 MUX
Total number of variables = 4 (A, B, C, D)
Select line = 1 (D)
Inputs = 3 (A, B, C)
I₀ = ABC + ABC + ABC
= AC + (B + B) + ABC
= AC + ABC
I₁ = ABC + ABC + ABC + ABC + ABC
= (A + A) BC + ABC + ABC + ABC
= BC + ABC + AC (B + B)
= BC + ABC + AC
Example 5.  Implement the following boolean function with 8 : 1 multiplexer.
F (A, B, C, D) = II M (0, 1, 3, 5, 8, 12, 15)
Sol.   Firstly convert the given maxterm into minterms :
F (A, B, C, D) = m (2, 4, 6, 7, 9, 10, 11, 13, 14)
Total number of variable = 4 (A, B, C, D)
Number of inputs = 1 (A)
Select lines = 3 (B, C, D)
Implementation table
Example 6. Implement the following boolean funtion with 8 : 1 multiplexer.
F (A, B, C, D) = m (0, 2, 3, 4, 7, 8, 15) + d (1, 5, 6, 10, 11)
Sol. Total number of variables = 4 (A, B, C, D)
Select line = 3 (B, C, D)
Input line = 1 (A)
Demultiplexer
A decoder with an enable input can function as a demultiplexer. A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2ⁿ possible output lines.
1 to 4 Demultiplexer
In 1 to 4 demultiplexer 1 represente demultiplexer input and 4 represents the number of output lines. thus, 2 (2⁴ = 4) select lines is required to construct 1 to 4 demultiplexer.
Block Diagram of 1 to 4 DEMUX
Example 7. Implement the full adder by using 1 to 8 demultiplexer.
Sol. Truth table of full adder
In terms of minterms it can be represented as.
Sum = m (1, 2, 4, 7)
Carry = m (3, 5, 6, 7)
The implemention of full adder using demultiplexer shown below :
Parity Generator
A parity generator is combinational logic circuit that generates the parrity bits. a parrity bit is an extra bit which is in the message can be either even or odd according to the parrity used. there are two types of generators and checkers :

1. Even parrity generator
2. Odd parrity generator

Even Parrity Generator
An even parrity generator is a combinational circuit that generator a word which always contain even number of 1’s let us consider an example of 4 bit information with even parrity.
K-map for p with inputs A, B, C and D
P = n (1, 2, 4, 7, 8, 11, 13, 14)
P = A . B . C . D
Logic Diagram of Even Parity Generator

2. Odd Parity generator

Odd parity generator is a combinational circuit that generator a word which always contain odd number of 1’s let us consider an example of 4 bit information with odd parity
Parity Checker
At the receiving end a combinational logic circuit which checks the parity of inputs and provides the output of 1. for an even parity checker, if the parity of input message is even, then the output is zero. otherwise the output is 1.
After solving k-map for PE, we get
PE = A . B . C . D . P
Magnitude Comparators
The basic function of a magnitude comparator is to compare the magnitudes of two quantities in order to determine the relationship to those quantities. A comparator circuit determines whether two number are equal.
1 bit Magnitude Comparator
One bit comparator is a combinational logic circuit which compares the two binary inputs and given output.
From the truth table
(A > B) = AB
(A = B) = AB + AB = A .B
(A < B) = AB
2-bit Comparator
It is a comparator logic circuit used to compare 2 bit from each input.
(A > B) = A₀B₁ B₀ + A₁B_{1 +}  A₁A₀B_0
(A = B) = (A₀ B₀) (A₁ B₁)
(A < B) = A₁A₀B₀ + A₀B₁B₀ + A₁B₁
Programmable Logic Devices
A programmable logic devices is an IC that is user configurable and is capable of implementing logic fucntions. it is an LSI chip PLDs can be reprogrammed in a few second and hence, give more flexibility to experiment with designs.
Read Only Memory (ROM)
A read only memory (ROM) is a memory device in which permanet binary information is stored. the binary information is specified by the required interconnection pattern. once the pattern is established, it stays within the unit when the power is turned off and on again. it is used only for reading the information from it.
A ROM which can be programmed is called a PROM. the process of entering information in a ROM is known as programming ROMs are used to stor information which is of fixed type.
ROMs can be used for designing combinational logic circuits. Depending on the type of ROM used, a user can design and modify the ciruits easiy.
ROM Organization
A blok diagram of a ROM is shown in figure. it consists of k inputs and n outputs. the inputs provide the adderss from the memory and the outputs give the data bits of the stored word which is selected by the data bits of the stored word which is selected by the address. integrated circuit ROM chips have one or more enable inputs and sometimes come with three state outputs to facilitate the construction of large arrays of ROM.
Figure shows the internal logic construcion of the ROM. the five inputs are decoded into 32 distinct output by means of a 5 x 32 decoder. ROM is basically a decoder with k inputs and 2^k output lines followed by a bank of OR gates. each output of the decoder represents a memory address. the 32 outputs of the decoder are connected to each of the 8 OR gates.
Each OR gate has 32 input connections and there are 8 OR gates, the ROM contains 32×8 = 256 internal connections. in general. a 2^k x n ROM will have an internal k x 2^k decoder and n OR gates. each OR gate has 2^k inputs, which are connnected to each of the outputs of the decoder.
The programmable intersection between two lines is sometimes called a cross poiint.
Example 8.   Design a combinational circuit using a ROM. the circuit accpepts a 3 bit number and generates an output binary number equal to the square of the input number.
Sol.  The fist step in the design is to derive the truth table of the combinational circuit. in most cases this is all that is needed. in other cases, we can use a partial truth table for the ROM by utilizing certain properties in the output variables.
The minimum size ROM needed must have three inputs and four outputs. three inputs specify eight words, so the ROM must be size 8 x 4. the ROM implementation is shown in figure. the three input specify eight words of 4 bit each. the ROM truth table in fig. (a) specifies the information needed for programming the ROM . the block diagram of fig. (b) shows the required connections of the combinational circuit.
B₅ = m (6, 7)
B₃ = m (3, 5)
B₂ = m (2, 6)
B₁ = 0
B₀ = m (1, 3, 5, 7) = A₀
(a) ROM truth table
Types of ROMS
There are two types of semiconductor technologies used for the manufacturing of ROM ICs. First one is bipolar technolgy and another is MOS dechnology which use bipolar devices and MOS devices and MOS devices respectively. the process of entering information into a ROM is called programming the ROM. bipolar ROMs and MOS ROMs use different techniquse of programming. depending upon the programming process used, the ROMs are categorzed as follows
Mask Programmable Read Only Memory (MROM)  In this type of read only memory (ROM), the user specifies the data to be stored to the manufacturer of the memory. the data patterm specifed by the user are programmed as a part of the fabrication process. once programmed, the data pattern cannot be changed. this type of read only memory is referred to as ROM.
Programmable Read Only Memory (PROM)  In this type of memory the datab pattern is programmed electrically by the user using a special circuit known as PROM programmer. it can be programmed, the data cannot be altered. this type of memory is known as PROM.
Erasable Programmable Read Only Memory (EPROM)   In this type of memory, data can be written any number of times means they are reprogrammable.before it is reprogrammed, the contents already stored are erased by exposing the chip to ultraviolet radiation for about 30 minute. this type of memory is referred to as EPROM. EPROMs are possible only in MOS technolgy, programming is done using a PROM programmer.
Electrically Erasable and Programmable Read Only Memory (EEROM or E² PROM) This is another type of reprogrammable memory in which erasing is dose electrcally rather than exposing the chip to the ultraviolet radiation. it is referred to asEEPROM or electrically alterable ROM (EAROM).
Combinational Progra-mmable Logic Devices
A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of products implementation. there are three major types of combinational PLDs and they differ in the placement of the programmable connection in the AND-OR array. the various PLDs used are PALs (programmable array logics), PLAs (programmable logic arrays) and PROMs (programmable read only memories).
The most flexible PLD is the programmable logic array (PLA) where both the AND and OR arrays can be programmed.
Programmable Array Logic (PAL)
PAL is a PLD with a fixed OR array and a programmable AND array. because only the AND gates are programmable, the PAL is easier to program but is not as flexible as the PLA some manufacturers also allow output inversion to be programmed. thus, like AND-OR and AND-OR-INVERT logic, they implement a sum of products logic funtion.
The actual PAL circuits have several groups of AND gates, each group providing inputs to separte OR gates.
It is difficult to show the implementation of PAL in the above connected and disconnected fuse form. for simplifying, if inputs to the OR gates at the outputs are fixed as shown by x marked on the vertical lines. the inputs to the AND gates are marked on the corresponding line by the x removing the x implies blowing-off the corresponding fuse which in turn implies that the corresponding input variable is not applied to the particular AND gate. in this example, the circuit is unprogrammed because all the fusible links are intact.
simplified method for showing connections in PAL circuits
Note that, the 3-input OR gates in fig. (c) are also drawn with a single input line.
Example 9. Implement the following boolean functions using PAL with four inputs and 3-wide AND-OR structure. Also write the PAL programming table.
F₁(A, B, C, D) = m (2, 12, 13)
F₂(A, B, C, D) = m (7, 8, 9, 10, 11, 12, 13, 14, 15)
F₃(A, B, C, D) = m (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
F₄(A, B, C, D) = m (1, 2, 8, 12, 13)
Sol. The k-maps for the above expressions, their minimization and the minimal expressions obtained from them are shown in figure. note that the function for F₄ has four product tems. the logical sum of two of these terms is equal to F₁ By using F₁ it is possible to reduce the number of terms for F₄ from four to three. the implementation of the minimal logic expressions using PAL is shown in figure.
The fuse map for the PAL as specified in the programming table is shown in fig. (a) for each 1 or 0 in the table, we mark the corresponding intersection in the diagram with the symbol for an intact fuse. for each dash, we mark the diagram with blown fuses in both the true and complement inputs. if the AND gate is not used, we leave all its input fuses intact. since, the corresponding input receives both the true and complement of each input variable, we have AA = 0 and the output of the AND gate is always 0. usually a x inside the AND gate is used to indicate that all its inpu fuses are intact.
Sol.                   I_in(OFF) = 20 nA
V_in(off) = 0
(i) The differential input voltage
I_In(off) x 1 = 20 x 1 = 20 uV
(ii) If A = 10⁵, then the output offiset voltge
V_in(off) = 20 x 10⁵ = 2V
Output offset voltage = 2V
Ideal Voltage Transfer Curve
The graphic representaion of the output equation is shown in fig. 31 in which the output voltage V₀ is plotted against differential input voltage V_D, keeping gain A_d constant.
The output voltage cannot exceed the positive and negative saturation voltages. these saturation voltage are specified for given values of supply voltages. this means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage remains constant.
Thus, curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. if the veritcal because of very large values of A_d.
OPen-Loop Op-amp Configuration
In the case of amplifiers, the term open-loop indicates that no connection exists beteen input and output terminals of any type. that is, the output signal is not feedback in any form as part of the input signal.
In open-loop configuration the op-amp functions as a high gain amplifier. there are three open-loop op-amp configurations.
The Differential Amplifier
Fig. 32 shows the open loop differential amplifier in which input signals V_in are applied to the positive and negative input terminals.
Since, the op-amp amplifiers the difference the batween the two input signals, this configuration is called the differential amplifier. the op-amp amplifies both AC and DC input signals. the source resistance R_{in 1} and R_{in 2} are normally negligble compared to the input resistance R_i therefore, voltage drop across these resistance can be assumed to be zero.
Therefore,             V₁ = V_{in 1} and V₂ = V_{in 2}
V₀ = A_d (V_{in 1} – V_{in 2})
Where, A_d is the open-loop gain.
The Inverting Amplifier
If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is called inverting amplifier. this configuration is shown in fig. 33.
The negative sign indicates that the output voltage is out of phase w. r. t. input 180⁰ or is of opposite polarity. thus, the input signal is ampliffied and inverted also.
The Non-Inverting Amplifier
In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is ground as shown in fig. 34.
V₁ = V_in,   V₂ = 0
V₀ = + A_dV_in
This means that the input voltage is amplified by A_d and there is no phase reversal reversal at the output.
In all there configurations, any input signal slightly greater than zero drive the output to saturation level. this is because of very high gain. thus when operated in open-loop, the output of the op-amp is either negative or positive saturation or switches between positive and negative saturation levels. therefore, open-loop op-amp is not used in linear applications.