Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V

know the answer question Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V ?
Common Data/Linked Answer Questions
Common Data for Questions 1 and 2
Consider the common emitter amplifier shown below with the following circuit parameters :
B = 100, g_m = 0.3861 A/V
r_o = _oo, = 259 k, R_S = 1K
R_B = 93 K, R_C = 250
R_L = 1K, C₁ = ₀₀ and C₂ = 4.7 mF

1. the resistance seen by the source V_S is

(a) 258
(b) 1258
(c) 93 k
(d) infinite

2. the lower cut-off frequency due to c₂ is

(a) 33.9 Hz
(b) 27.1 Hz
(c) 13.6 Hz
(d) 16.9 Hz
Statements for linked answer questions 3 and 4
Consider the CMOS circuit shown, where the gate voltage V_G of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V. assume that for both transistors, the magnitude of the threshold voltage is 1 V and the product of the trans conductance parameter and the (W/L) ratio, i.e. the quantity _uC_ox  (W/L) is 1mA/V^-2

3. For small increase in V_G beyond 1 V, which of the following gives the correct description of the region of operation of each MOSFET?

(a) both the MOSFETs are in saturation region
(b) both the MOSFETs are in triode region
(c) n-MOSFET is in triode and p-MOSFET is in saturation region
(d) n-MOSFET is in saturation and p-MOSFET is in triode region

4. Estimate the output voltage V_O for V_G = 1.5 V.

[Hint Use the appropriate current voltage equation for each MOSFET, based on the answer to question 3]
(a) 4 – 1/2 V
(b) 4 + 1/2 V
(c) 4 – 3/2 V
(d) 4 + 3/2 V
Statements for linked answer questions 5 and 6
In the following transistor circuit V_BE = 0.7 V, r = 25 mV/I_E and B and all the capacitances are very large.

5. the value of DC current I_E is

(a) 1 mA
(b) 2 mA
(c) 5 mA
(d) 10 mA

6. the mid- band voltage gain of the amplifier is approximately

(a) – 180
(b) – 120
(c) – 90
(d) – 60
Statements for linked answer questions 7 and 8
Consider the op-amp circuit shown in the figure.
 

7. the transfer function V₀(s) V_I (s) is

(a) 1-sRC/1+sRC
(b) 1 + sRC/1 – sRC
(c) 1/1-sRC
(d) 1/1+ sRC

8. If V_I = V₁ sin (₀₀t) and V_O = V₂ sin (₀₀t + ₀) then the minimum and maximum values of (in radian) are, respectively

(a) -2/and 2
(b) 0 and 2
(c) – and 0
(d) -2 and 0
Common data for questions 9, 10 and 11
In the transistor amplifier circuit shown in the figure below, the transistor has the following parameters
B_DC = 60, V_BE = 0.7 V, h_w – ₀₀
the capacitance C_C can be assumed to be infinite.
in the figure above, the ground has been shown by the symbol.

9. Under the DC conditions, the collector to emitter voltage drop is

(a) 4.8 V
(b) 5.3 V
(c) 6.0 V
(d) 6.6 V

10. If B_DC is increased by 10% the collector to emitter voltage drop

(a) increases by less than or equal to 10%
(b) decreases by less than or equal to 10%
(c) increases by more than 10%
(d) decreases by more than 10%

11. the small-signal gain of the amplifier is

(a) -10
(b) -5.3
(c) 5.3
(d) 10
In the figure above, the ground has been shown by the symbol.

12. the power dissipation in the transistor Q₁ shown in the figure is

(a) 4.8 w
(b) 5.0 w
(c) 5.4 w
(d) 6.0 w

13. If the unregulated voltage increases by 20%, the power dissipation across the transistor Q₁

(a) increases by 20%
(b) increases by 50%
(c) remains unchange
(d) decreases by 20%
Common data for questions 14 and 16
Given, r_d = 20 k, I_DSS = 10 mA, V_P = – 8 V

14. Z_I and Z_O of the circuit are, respectively

(a) 2 M and 2 k
(B) 2 M and 20/11 k
(c) infinite and 2 k
(d) infinite and 20/11 k

15. I_D and I_DS under DC conditions are, respectively

(a) 5.625 mA and 8.75 V
(b) 7.500 mA and 5.00 V
(c) 4.500 mA and 11.00 V
(d) 6.250 mA and 7.50 V

16. transconductance in milli-siemen (mS) and voltage gain of the amplifier are, respectively

(a) 1.875 mS and 3.41
(b) 1.875 mS and -3.41
(c) 3.3 mS and -6
(d) 3.3 mS and 6
Statement for linked answer questions 17, 18 and 19
Consider the circuit shown below, assume that diodes are ideal.

17. If V₁ = 10 V and V₂ = 5 V, then output voltage V_O is

(a) 9 V
(b) 9.474 V
(c) zero
(d) 8.943 V

18. If V₁ = V₂ = 10 V_, then output voltage V_O is

(a) 9 V
(b) 9.474 V
(c) 4 V
(d) 8.943 V

19. If V₁ = – 5 V and V₂ = 5 V, then V_O is

(a) 9.474 V
(b) 8.943 V
(c)4.5 V
(d) 9 V
Statement for linked answer questions 20 and 21
Consider the circuit shown below. assume diodes are ideal.

20. If V₁ = V₂ = 10 V, then output voltage V_O is

(a) zero
(b) 9.737 V
(c) 9 V
(d) 9.5 V

21. If V₁ = -5 V and V₂ = 10 V, the output voltage V_O is

(a) 9 V
(b) 9.737 V
(c) 9.5 V
(d) 4.5 V
Statement for linked answer questions 22 and 24
The diodes in the circuit shown below have linear parameters of V_D = 0.6 V and r_f = 0.

22. if V₁ = 10 V and V₂ = 0 V, then V_O is

(a) 8.93 V
(b) 7.82 V
(c) 1.07 V
(d) 2.18 V

23. If V₁ = 10 V and V₂ = 5 V, then V_O is

(a) 9.13 V
(b) 0.842 V
(c) 5.82 V
(d) 1.07 V

24. If V₁ = V₂ = 0, then output voltage V_O is

(a) 0.964 V
(b) 1.07 V
(c) 10 V
(d) 0.842 V
Statements for linked answer questions 25 and 26
the diode in the circuit shown below has the non-linear terminal characteristics as shown in figure. let the voltage be V_S = cos ₀₀t V.

25. the current I_D is

(a) 2.5 (1 + cos ₀₀t) mA
(b) 5(0.5 + cos _oot) mA
(c) 5( 1 + cos ₀₀t) mA
(d) 5(1 + 0.5 cos ₀₀t) mA

26. the voltage V_D is

(a) 0.25(3 + cos ₀₀t) V
(b) 0.25 (1 + 3 cos ₀₀t) V
(c) 0.5 (3 + 1 cos ₀₀t) V
(d) 0.5 (2 + 3 cos ₀₀t) V
Statement for linked answer questions 27 and 29
in the voltage regulator circuit shown below the zener diode current is to be limited to the range 5 < I_Z < 100 mA.

27. the range of possible load current is

(a) 5 < I_L < 130 mA
(b) 25 < I_L < 120 mA
(c) 10 < I_L < 110 mA
(d)none of these

28. the range of possible load resistance is

(a) 60 < R_L < 372
(b) 60 < R_L < 200
(c) 40 < R_L < 192
(d) 40 < R_L < 360

29. the power rating required for the load resistor is

(a) 576 mW
(b) 360 uW
(c) 480 mW
(d) 75 uW
Statement for linked answer questions 30 to 32
for the transistor in circuit shown below B = 200.

30. if V_B = 0 V, the value of I_E and V_C are

(a) 6.43 mA, 2.4 V
(b) 2.18 mA, 3.4 V
(c) 0,6 V
(d) none of these

31. If V_B = 1 V, the value of V_C is

(a) 4 V
(b) 3 V
(c) 1 V
(d) 1.9 V

32. if V_B = 2 V , the value of V_C is

(a) – 7 V
(b) 1.5 V
(c) 2.6 V
(d) none of these
Statement for linked answer questions 33 to 35
the transistor in circuit shown below has B = 200.

33. If V_BB = 0, the value of voltage V_O is

(a) 2.46 V
(b) 1.83 V
(c) 3.33 V
(d) 4.04 V

34. if V_BB = 1 V , the value of voltage V_O is

(a) 4.11 V
(b) 1.83 V
(c) 2.46 V
(d) 3.44 V

35. if V_BB = 2 V, the value of voltage V_O is

(a) 3.18 V
(b) 1.46 V
(c) 0.2 V
(d) none of these
Statement for linked answer questions 36 and 37
Consider the circuit given in figure below, it is given that I_SI = 2 I_S2 = 5 x 10^-16 a.

36. if I₁ = 1.2 mA, the value of V_B is

(a) 731.1 mV
(b) zero
(c) 730.6 mV
(d) 1.5 mV

37. if circuit is at the edge of active region, what is the value of R_C ?

(a) 1475 k
(b) 4.95 k
(c) 0.1 k
(d) none of these
Statement for linked answer questions 38 and 39
Consider the transistor amplifier circuit shown below. the transistor parameters are given as B = 100. V_BE (on) = 0.7 V. V_A = ₀₀

38. Current gain A_I = I_O/I₁ is

(a) 0.48
(b) 1.00
(c) 0.92
(d) 0.98

39. Voltage gain A_V = V_O/V_S is

(a) 177.1
(b) 345.2
(c) 50
(d) 384.6
Statement for linked answer questions 40 and 41
in the given darlington pair circuit of figure p 120, transistor Q₁ and Q₂ parameters are B₁r₁ and B₂r₂ respectively.

40. the current gain A_I = I_O/I₁ of the circuit is

(a) B₁B₂
(b) B₁ + B₂
(c) B₁ + B₂ + B₁B₂
(d) B₁ + B₂ – B₁B₂

41. input impedance R_IN is

(a) r₁ + r₂
(b) r₁ + (1 + B₁) r₂
(c) B₁ r₁ + B₂ r₂
(d) (1 + B₁) r₁ + r₂
Statement for linked answer questions 42 and 43
for the p-channel transistor in the circuit shown below the parameters are I_DSS = 6 mA, V_P = 4 V and = 0

42. the value of I_DQ is

(a) 8.86 mA
(b) 6.39 mA
(c) 4.32 mA
(d) 1.81 mA

43. the value of V_SD is

(a) -4.28 V
(b) 2.47 V
(c) 4.28 V
(d) 2.19 V
Statement for linked answer questions 44 and 45
for the following circuit transistor parameters are I_DSS = 6 mA, V_P = – 6 V, B = 100, V_BE = 0.7 V.

44. Voltage V_C nearly equals to

(a) 5.67 V
(b) 0.73 V
(c) 1.2 V
(d) 10.93 V

45. V_DS is nearly equal to

(a) 11.42 V
(b) 5.75 V
(c) 0.49 V
(d) 10.2 V
Statement for linked answer questions 46 and 47
An n-channel JFET amplifier circuit is shown in figure.
transistor parameters are given as
I_DSS = 12 mA, V_P = – 4 V = 0.008 V^-1

46. small-signal transconductance g_m is

(a) 9.01 mA /V
(b) 1.5 mA/V
(c) 4.5 mA/V
(d) 2.98 mA/V

47. small-signal voltage gain A_V = V_O /V_S is

(a) -9.25
(b) -27.72
(c) -4.62
(d) -41.58
Common data/Linked Answer Questions

1. (b)

the low frequency model
r_e = 25 mV/I_C
= 2.59
the resistance seen by the source
Z_IN = R_S + (R_B||B_RE)
= R_S + [R_B x Br_e/R_B + Br_e
= 10³ + (93 x 10³ x 100 x 2.59/93 x 10³ + (100 x 2.59)
= 10³ + 258 – 1258

2. (b)

the lower cut-off frequency
f_l = 1/2 (R_L + R_C)C₂
1/2 (10³ + 2.50) (4.7 x 10^-6)
1/2 x 1250 x 4.7 x 10^-6 = 27.1 Hz

3. (a)

given, that threshold voltage for p-MOS = 1 V
Gate voltage is 3 V. hence, the p-MOS is in active region.
whereas the threshold voltage for n-MOS = 1 V
When gate voltage V_G is increased from 1 V. the n-MOS is in saturation.

4. (b)
5. (a) For DC analysis, all capacitors become open circuited. thevenin equivalent of circuit

When, V_TH = 10/10 + 20 x 9 V (from voltage divider rule)
= 3 V
and     R_TH = 101120 = 10 x 20 /10 + 20 = 6.67 k
As B is very large, I_B can be ignored.
Applying KVL in base emitter loop,
V_TH – V_BE = I_ER_E
I_E = V_TH – V_BE/R_E = 1 mA

6. (d)

the small signal model
g_m = |I|/V_T = I_E/V_T = 1mA/25 mV = 1/25 A/V
V_O = -g_mV_in (3k ||3k)
= – 1/25 x V_in x 1.5 k
A_V = V_O/V_IN = – 60

7. (a)

V_A = V_I x 1/sC
R + 1/sC
V_A = 1/1 + sRC   = V_I
From virtual ground concept
V_B = V_A = 1/ 1 + sRC = V_i
applying KCL at node B,
V_I – V_B /R₁ = V_B – V_O/R₁
Putting the value of V_B,
V_o /V_I = 1 – sRC/ 1 + sRC

8. (c)

As       H (S) = V_O (s) /V_I (s) = 1 – sRC/ 1 + sRC
H (j₀₀) = 1 – j₀₀ RC/ 1 + j₀₀ RC
LH (i₀₀) = – tan ^-1 ₀₀ RC – tan ^-1 ₀₀RC
= – 2 tan^-1 ₀₀ RC
AT      ₀₀  – ₀₀
LH (j₀₀)_min
LH (j₀₀) _max = 0

9. (c)

Under DC condition, the circuit becomes
Applying KVL in collector emitter circuit,
12 – 1 k (I_C + I_B) – V_CE = 0
and in base loop.
V_CC – 1K (I_C + I_B) – 5I_B – V_BE = 0
I_C = BI_B
Solving eqs. (1), (2) and (3), we get
V_CE = 5.95 V.

10. (b)

As given B increased by 10%.
now, B = 60 + 60 x 10/100 = 66
calculating V_CE for B = 66 as in previous question for  B = 60
V_CE = 5.69 V
% change = 5.69 – 5.95 /5.95 x 100
= – 4.37%

11. (a)
12. (c)

Zener diode is in breakdown, hence
V_A = 6 V
V₀₁ = (1 + R_F/R₁) V_A (non-inverting amplifier)
Here,     R_F = 12 K , R₁ = 24 K
V_O1 = 9 V
V_CE = 15 – 9 = 6 V
I_C = V₀₁/R_L = 9/10 = 0.9 A
Power dissipated in Q₁
= V_CE x I_C = 6 x 0.9 = 5.4 W

13. (b)

As V_Z is 6 V.
the V₀₁ and I_C will be same.
V_OR = 15 + 15 x 20 100 = 18 V
V_CE = 18 – 9 = 9 V
P_D = V_CE x I_C = 9 x 0.9 = 8.1 W
% increase = 8.1 – 5.4 /5.4 x 100% = 50%

14. (b)

the small signal model
Z_IN = 2M
Z_O = 20 K||20 K = 20/11 K

15. (a)

V_GS = – 2 V < 0, hence FET is operating in active region.
I_D = I_DSS (1 – V_GS/V_P)²
= 10 (1 – (-2)/(-8))² = 5.625 mA
V_DS = V_DD – I_DR_D
= 20 – 5.625 x 10^-3 x 2 x 10³ = 8.75 V

16. (a)

g_m = 2/|V_P|I_D I_DSS = 1.875 mS
A = g_m (r_a||R_D)
= 1.875

17. (d)

Assume D₁ On and D₂ off
then, V_O = 9/1 + 9 V₁ = 9 V
Check assumption
I_D1 = V₁ – V_O/1 = 10 – 9 = 1 mA > 0
Therefore, D₁ on
V_D2 = V₂ – V₀

18. (b)

assume D₁ and D₂ on,
10/1 + 10 /1
v_o = 1/1 + 1/1 + 1/9 = 9.474 V
check assumption
I_D1 = I_D2 = V₁ – V_O/1
= 10 – 9.474 /1 = 0.526 > 0
Therefore, D₁ and D₂ on,

19. (c)

assume D₁ off and D₂ on
V_O = 9/9 + 1 V₂ = 9/9 + 1 (5) = 4.5 V
check asspumption
I_D2 = V₂ – V_O/1 = 5 – 4.5 = 0.5 > 0
therefore, D₂ on
V_D1 = V₁ – V_O = – 5 – 4.5 = – 9.5 < 0
Therefore D₁ off

20. (b)

assume D₁ and D₂ on
10/1 + 10/1 + 5/9
V_O = 1/1 + 1/1 + 9/1 = 9.737 V
1 + 1 + 9

21. (c)

assume D₁ off and D₂ on,
10/1 + 5/9
V_O = 1/1 + 9/1 = 9.5
Check assumption
U_D2 = 10 – 9.5 /1 = 0.5 A > 0
Therefore D₂ on
V_D1 = V₁ – V_O = -5 – 9.5 = – 1.45 < 0
Therefore D₂ off.

22. (c)

D₁ Will be off and D₂ Will be on,
10 = 95I + 0.6 + 0.5I
I = 0.94 mA
V_O = 10 – 9.5 x 0.94 = 1.07 V

23. (c)

D₁ will be off and D₂ will be on.
10 = 9.5i + 0.6 + 0.5i + 5       i = 0.44 mA
V_O = 10 – 9.4 i = 5.82 V

24. (d)

both D₁ and D₂ will be on and I_D1 = I_D2 = 1/2
10 = 9.5i +0.6 + 0.5 i/2     i = 0.964 mA
V_O = 10 – 0.964 (9.5) = 0.842 V

25. (c)

the thevenin equivalent circuit for the network to the left of terminal ab is shown below
V_TH = 100/200 (2 + cos ₀₀t) = 1 + 0.5 cos ₀₀t V
R_TH = (100)²/200 = 50
The diode can be modeled with V_F = 0.5 V and
r_f = 0.7 – 0.5 /0.004 = 50
I_D = V_TH  – V_F/R_TH + r_f = 1 + 0.5 cos – 0.5 /50 + 50
= 5 (1 + cos _oot) mA

26. (a)

V_D = R_FI_D + V_F
= 50 x 5(1 + cos _oot) x 10^-3 + 0.5
= 0.75 + 0.25 cos _oot = 0.25 (3 + cos ₀₀t) V

27. (b)

current through 12 resistor is
I = 6.3 – 4.8 /12 = 125 mA
I_L = I – I_Z = 125 – I_Z
25 < I_L < 120 mA

28. (c)

25 < I_L < 120 mA I_LR_L = 4.8 V
25 < 4.8/R_L < 120 mA
40 < R_L < 192

29. (a)

P_L = I_LV_Z = (120m) (4.8) = 576 mW
 

30. (c)

V_B = 0, transistor is in cut-off region
I_E = 0, V_C = 6 V

31. (b)

V_B = 1 V. I_E = 1- 0.7/1 K = 0.3 mA
I_C = I_E = 0.3 mA
V_C = 6 – I_CR_C = 6 – (0.3 ) (10) = 3 V

32. (b)

V_B = 2 V, I_E = 2 – 0.7/1 = 1.3 mA
I_C = I_E = 1.3 mA
V_C = 6 – (1.3) (10) = – 7 V
Transistor is in saturation. the saturation voltage
V_CE = 0.2 V
V_E = (1.3) (1) = 1.3 V
V_C = V_CE + V_E = 1.5 V

33. (c)

V_BB = 0, Transistor is in cut -off region
V_C = R_L /R_C + R_L V_CC = 10 (5) /10 + 5 = 3.33 V

34. (b)

I_B = 1 – 0.7/50K = 6 uA
I_C = BI_B = 75 x 6u = 0.45 mA
5 – V_O/5K = I_C + V_O/10K
(1 – 0.4) = V₀/5 + V_O/10
V_O = 1.83 V

35. (c)

I_B = 2 – 0.7/50K = 26 uA
I_C = BI_B  = 75 x 26 uA = 1.95 mA
V_C = 5 – I_CR_C = 5 – 5 x 1.95 = – 4.75 V
Transistor is in saturation,
V_CE = 0.2 V = V_C = V_O

36. (c)

from the circuit, we get
I₁ = I_C1 + I_C2
I_C1 = I_S1 e^vb/v2t,         I_C2 = I_S2 e^ve/vt
so, I₁ = I_S1 e^ve/vt + I_C2 = I_S2 e^ve/vt
= (I_S1 + I_S2) e^vb/ve
= (5 x 10^-16 + 5/2 x 10^-16)e^vb/vt
As,  I_S2 = I_S2/2 = 5/2 x 10^-16
also, I₁ = 1.2 mA
So, 1.2 x 10^-3 = 5 x 3/2 x 10^-16 e^vb/26×10-3
V_T = 26 x 10^-3V
2 x 1.2 x 10^-3/15 x 10^-16 = e^vb/26×10-3
2.4 x 10¹³/15 = e^{vb/26 x 10-3}
V_B = 26 x 10^-3 in (2.4/15 x 10¹³) = 730.6 mV

37. (b)

by applying KVL
V_CC – I_CR_C – V_C = 0
R_C = V_CC – V_C/I₁
As, transistor is at edge of active mode.
so, V_S = V_C     R_C = V_CC – V_B/I₁ = 1475

38. (d)

by DC analysis of the circuit
I_EQ = 10 – 0.7 /(10K) = 0.93 mA
I_CQ = (B/B + 1) I_EQ = 100 /101 x 0.93 = 0.921 mA
r = BV_T/I_CQ = (100)(0.026)/0.921 = 2.82 K
g_m = I_CQ/V_T = 0.921/0.026 = 35.42 mA/V
By small signal AC analysis of the circuit
I_O = g_mV
apply KCL at emitter
I₁ = V/T + V_S/R_E + g_mv
I₁ = V_S/R_E||r + g_mv_s = v_s(1/R_E||r + g_m)
current gain
A_I = I_O/I₁ = g_mV_s = g_m(R_E||R) /1 + g_m (R_E ||r)
= (35.42)(10 k||2.82 k)/1 + (35.42) (10k||2.82 k) = 0.98

39. (a)

from small signal AC -equivalent circuit
V_O  = g_mVR_C = g_mV_SR_C
A_O = V_O/V_S = g_mR_C
= (35.42 mA/V)(5 K) = 177.1

40. (c)

small signal equivalent circuit of the darlington-pair
V₁ = I₁ R₁
So, g_m1V₁ = gm₁ r₁i₁ = B₁i₁ …………………(1)
                                                                                 (B₁ = g_m1 r₁)
V₂ = (i₁ + g_m1 v₁) r₂ = (i₁ + B₁I₁) r₂ ………………….(2)
putting V₁ and V₂ from eqs, (1) and (2)
i_o = g_m1 r₁i₁ + g_m2 (i₁ + B₁I₁) r₂
i_o = B₁ i + g_m2 (i₁ + B₁ i₁) r₂
i_o = B₁ + g_m2r₂ + g_m2 r₂ B₁
i_o/i₁ = B₁ + B₂ + B₁B₂
So,    A_I = I_O/I₁ = B₁ + B₂ + B₁B₂

41. (b)

from equivalent circuit
V_S = V₁ + V₂ = i₁r₁ + i₁ (1 + B₁)r₂
R_in = V_S/F₁ = r₁ + (1 + B₁) r₂

42. (d)

assume transistor is in saturation
V_S = – V_GS
I_D = 0 – V_S/R_S = V_GS/R_S = I_DSS (1 – V_GS/V_P)²
R_S = 1K
V_GS/1 K (6 M) (1 – V_GS/4)²
V_GS = 8.86, 1.81 V
V_GS = 8.86 V is impossible
I_D = V_GS /R_S = 1.81/1K = 1.81 mA

43. (b)

V_D = I_DR_D – 5 (1.18m) (0.4 k) – 5 = – 4.276 v
V_SD = V_S – V_D = – 1.81 – (-4.276) = 247 V
V_SD(SAT) = V_P – V_GS = 4 – 1.81 = 2.19 V
V_SD > V_SD(SAT)
Assumption is correct.

44. (a)

assuming base current is zero,
V_B = V_G = 10K (16)/(40K + 10K) = 3.2 V
V_E = V_B – V_BE = 3.2 – 0.7 = 2.5 V
I_E = V_E/R_E = 2.5/1.2K = 2.08 mA
I_C = I_E = 2.08 mA
I_D = I_C = 2.08 mA
V_C = V_G – V_GS
Where, V_GS = V_P (1 = I_D/I_DSS)
V_C = (-6) (1 = 2.08/6) = – 2.47 V
V_C = 3.2 – (-2.47) = 5.67 V

45. (b)

from the circuit
V_D = 16 – I_D (2.2) = 11.42 V
V_DS = V_D – V_S = V_D – V_C
11.42 – 5.67 = 5.75 V

46. (d)

By DC analysis of the circuit
V_GS = (180/180 + 420) 20 – I_D x 2.7
I_D = I_DSS (1 – V_GS/V_P)²
So,   V_GS = 6 – I_DSS (1 – V_GS/V_P)² x 2.7
V_GS = 6 – (12) (2.7) (1 – V_GS/(-4)²
2.025 V²_GS = 17.2 V_GS + 2.4 = 0
V_GS = – 2.01 V
transconductance is
g_m = 2I_DSS/|V_P| (1 – V_GS/V_P)
= 2 (12) /4 [1 – (2.01)/(-4) ) = 2.98 mA/V

47. (c)

the small signal equivalent circuit of n-channel JFET is the same as n-channel MOSFET
Here,  R₁ = 420 K, R₂ = 180 K, R_D = 2.7 K
R_L = 4 K
Voltage gain
A_V = V_O/V_S = – g_m (r_o||R_D||R_L)
Output resistance
r_o ~ 1/I_D
BY DC analysis
I_D = I_DSS (1 – V_GS/V_P)² = 12 (1 – (-2.01)/(-4))²
= – 2.97 mA
So,   r_o ~ 1/ 0.008 x 2.97 = 42.1 k
A_V = – 2.98 (42.1||2.7||4) = – 4.62